ASIC Design Flow

An application-specific integrated circuit (ASIC) design flow is the structured sequence of processes and methodologies used to design and fabricate an integrated circuit tailored for a particular application, rather than for general-purpose use. This flow transforms a system specification or concept into a physical, manufacturable chip layout, encompassing stages from high-level architectural definition down to final verification and tape-out for semiconductor foundry production. ASIC design is a critical discipline within electronic design automation (EDA), enabling the creation of highly optimized, power-efficient, and cost-effective solutions for everything from consumer electronics to aerospace systems. The flow is characterized by a top-down, hierarchical approach that progresses through several major phases. It typically begins with system-level specification and architectural design, followed by register-transfer level (RTL) coding using hardware description languages (HDLs) such as Verilog or VHDL, which are used to describe the hardware's behavior and structure [5]. For mixed-signal designs, which integrate both digital and analog circuitry, extensions like Verilog-AMS or the IEEE Standard VHDL Analog and Mixed-Signal Extensions (VHDL-AMS) are employed [2][3]. These stages are supported by specialized modeling techniques; for instance, Wreal (wired-real) modeling in Verilog-AMS allows for the efficient representation of continuous analog behavior using discrete sampled real values [6]. The RTL description is then synthesized into a gate-level netlist, which undergoes physical design processes including floorplanning, placement, routing, and timing closure. Verification is a continuous, parallel activity throughout the flow, utilizing simulation, formal methods, and debug systems like the Verdi Automated Debug System to perform protocol-oriented performance analysis and ensure functional correctness [4]. The final output is a detailed set of files, such as a GDSII stream or a Circuit Description Language (CDL) netlist, which describes the electronic circuit for manufacturing [8]. The significance of the ASIC design flow lies in its ability to realize complex, high-performance systems on a single silicon die. It enables the integration of billions of transistors, as seen in advanced memory technologies like Samsung's V-NAND, which stacks 24 vertical layers [3]. The methodology's reliance on abstraction, automation, and reuse—such as employing part templates and global power nets for multi-chip distribution—is essential for managing design complexity and accelerating time-to-market. Modern flows increasingly incorporate system-level modeling with tools and languages like MyHDL, an open-source Python package, for early validation and architectural exploration [1]. The structured nature of the ASIC design flow is fundamental to the ongoing advancement of semiconductor technology, underpinning innovations in computing, telecommunications, and embedded systems across the global electronics industry.

Extracted References

Circuit Description Language (CDL) as a Netlist Format

Circuit Description Language (CDL) serves as a specialized netlist format for describing electronic circuits at the transistor or gate level [14]. Unlike behavioral or architectural description languages, CDL operates at a lower abstraction level, specifying the precise connectivity between components, including transistors, resistors, capacitors, and logic gates [14]. This format is crucial for tasks requiring detailed circuit representation, such as circuit simulation, layout generation, and formal verification against a schematic. A typical CDL file structure includes declarations for subcircuits, followed by the main circuit definition listing all component instances and their node connections [14]. For example, a simple CMOS inverter might be described by specifying the PMOS and NMOS transistors, their drain, gate, and source terminals, and their connections to power (VDD), ground (VSS), input, and output nodes [14]. The language syntax often supports parameters for components, allowing for the specification of transistor widths (e.g., W=2u) and lengths (e.g., L=0.18u) to define their electrical characteristics [14]. This level of detail is essential for accurate simulation of timing, power consumption, and signal integrity before physical implementation.

MyHDL: Python-Based Hardware Description and Verification

MyHDL represents a significant departure from traditional hardware description languages (HDLs) like VHDL and Verilog by leveraging the Python programming language ecosystem [13]. As an open-source, pure Python package, MyHDL enables hardware design and verification using Python's syntax and extensive libraries [13]. The core functionality transforms Python code constructs into a hardware description and verification language through a process of conversion and synthesis [13]. This is achieved by using Python decorators (e.g., @always, @instance) and specific data types (e.g., Signal, intbv) to describe concurrent processes and hardware registers that can be translated to synthesizable Verilog or VHDL code [13]. A key advantage is the ability to use Python's powerful features for verification, such as object-oriented programming for creating complex testbenches, and libraries like random and unittest for randomized testing and assertion checking [13]. For instance, a designer can write a finite state machine (FSM) controller in Python, simulate it with thousands of random input vectors, and then convert the verified design directly to gate-level netlists for synthesis [13]. This bridges the gap between high-level algorithmic modeling and low-level implementation, facilitating a more efficient verification flow.

IEEE Xplore as a Technical Literature Resource

The digital library IEEE Xplore provides comprehensive access to technical literature published by the Institute of Electrical and Electronics Engineers (IEEE) and its publishing partners [13]. It serves as a primary repository for peer-reviewed articles, conference proceedings, standards, and educational courses covering the breadth of electrical engineering, electronics, and computer science, including specialized topics in ASIC design methodologies [13]. For ASIC designers, it is an indispensable resource for researching state-of-the-art techniques in areas like behavioral synthesis, formal verification, and low-power design [13]. The platform's advanced search capabilities allow users to filter results by publication date, document type, and author, enabling efficient literature reviews [13]. Furthermore, many articles and standards hosted on IEEE Xplore are cited directly in commercial and academic design flows, providing authoritative references for implementation decisions and methodology validation [13].

Behavioral Synthesis Methodologies

Behavioral synthesis, also known as high-level synthesis (HLS), is a design automation step that converts an algorithmic description of a system's behavior into a register-transfer level (RTL) implementation [13]. This methodology allows designers to work at a higher abstraction level, using languages like C, C++, or SystemC to specify functionality, which is then automatically translated into a hardware structure consisting of a datapath (functional units, registers, multiplexers) and a controller (finite state machine) [13]. The synthesis process involves several key steps: resource allocation (deciding how many adders, multipliers, etc., are needed), scheduling (determining which operations occur in which clock cycle), and binding (mapping operations to specific hardware units and variables to registers) [13]. Optimization constraints, such as target clock frequency, area, and power, guide these steps. For example, a loop in a C description performing ten multiplications could be scheduled to use one multiplier over ten cycles (area-optimized) or ten multipliers in one cycle (performance-optimized) based on the designer's constraints [13]. This level of automation significantly accelerates the exploration of the design space for complex digital signal processing (DSP) or image processing cores.

The Layer Deposition Analogy in Process Flow

The initial stage of physical ASIC manufacturing is frequently analogized to the process of creating a layered cake, representing a fundamental challenge in the flow [13]. This analogy refers to the sequential deposition and patterning of various material films—such as silicon dioxide (SiO₂), polysilicon, and metal interconnects—on a pure silicon wafer substrate [13]. Each "layer" corresponds to a specific step in the front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. For instance, creating a transistor gate involves depositing a thin gate oxide layer (often just 1-2 nanometers thick), followed by a polysilicon layer, which is then patterned using photolithography and etching [13]. This step-by-step additive and subtractive process, alternating between deposition, lithography, and etching, builds the three-dimensional integrated circuit structure [13]. The precision required is extreme; misalignment between layers (overlay error) must typically be less than a few nanometers, and film thickness uniformity across a 300mm wafer must be within angstrom-level tolerances to ensure consistent device performance [13]. This intricate, multi-step sequence forms the physical foundation upon which all subsequent design and verification efforts are based.

Historical Development

The evolution of the ASIC design flow is inextricably linked to the advancement of semiconductor technology, electronic design automation (EDA) tools, and hardware description languages (HDLs). Its history reflects a transition from manual, transistor-level design to highly automated, system-level synthesis, driven by the increasing complexity and scale of integrated circuits.

Early Foundations and Manual Design (Pre-1980s)

Prior to the 1980s, ASIC design was a predominantly manual and schematic-driven process. Engineers designed circuits by drawing transistor-level schematics on paper or using early computer-aided design (CAD) systems for layout. The design flow was characterized by:

• Gate-level implementation: Designs were constructed from a library of pre-characterized logic gates (e.g., NAND, NOR, flip-flops) provided by the semiconductor foundry.
• Physical design by hand: The placement of these gates and the routing of interconnections between them were often done manually, a process prone to error and extremely time-consuming for circuits containing more than a few thousand transistors.
• Simulation limitations: Verification was rudimentary, relying on logic simulation at the gate level or even breadboarding discrete components for small sections of the design. There was no unified language to describe design intent at a higher level of abstraction. This era was defined by geometric design rules and layout editors, with the entire flow being highly integrated with a specific semiconductor manufacturer's process technology. The concept of a standardized, automated flow was virtually non-existent.

The HDL Revolution and the Rise of Verilog (1980s)

A paradigm shift began in the mid-1980s with the invention of hardware description languages. The most pivotal development was the creation of the Verilog HDL by Gateway Design Automation [15]. Phil Moorby, the principal designer, developed Verilog alongside the Verilog-XL logic simulator in 1984 [15]. This innovation introduced several transformative concepts to the ASIC flow:

• Behavioral modeling: Engineers could now describe the functionality and structure of a digital system using textual code at the Register Transfer Level (RTL), a significant abstraction above gate-level schematics. An RTL description specifies the flow of data between registers and the operations performed on that data.
• Simulation-driven verification: The accompanying Verilog-XL simulator allowed designers to test the behavior of their RTL code extensively before committing to physical implementation, dramatically improving verification quality [15].
• Technology independence: Initially, an RTL description in Verilog was largely independent of the underlying semiconductor technology. The same RTL code could, in theory, be synthesized into gates for different foundry processes, promoting design reuse. The commercialization and adoption of Verilog were accelerated when Cadence Design Systems acquired Gateway Design Automation in 1989, making Verilog a cornerstone of the EDA industry [15]. Concurrently, the VHDL language, developed under contract to the U.S. Department of Defense, emerged as a competing standard, further cementing the HDL-based methodology.

Advent of Logic Synthesis and Standard Cell Libraries (Late 1980s – 1990s)

The introduction of RTL design created a bottleneck: how to efficiently translate the high-level HDL code into a gate-level netlist. This was solved by the advent of commercial logic synthesis technology, most notably with Synopsys' introduction of its Design Compiler in the late 1980s. This tool automated the conversion of RTL code into an optimized gate-level netlist, a core pillar of the modern ASIC flow. This period saw the flow evolve to include:

• Standard cell-based design: Foundries began providing extensive standard cell libraries containing hundreds of pre-designed, characterized, and layout-optimized logic functions (inverters, complex gates, multiplexers, arithmetic units). The synthesis tool would select and interconnect cells from this library to implement the RTL design.
• The synthesis-then-place-and-route sequence: A clear sequential flow emerged: RTL design and simulation, followed by logic synthesis to a gate-level netlist, then physical placement and routing of the standard cells.
• Format standardization: The need to exchange netlist data between different EDA tools from various vendors led to the development of standard formats. One prominent example is the Circuit Description Language (CDL), a text-based netlist format used for representing transistor-level circuits and facilitating data exchange between design and verification tools [14]. The 1990s witnessed the full establishment of the RTL-to-GDSII flow, where GDSII became the industry-standard binary format for delivering the final mask data to the foundry. Automation increasingly handled placement and routing, though timing closure—ensuring the physical circuit met all speed requirements—became a major challenge as clock frequencies rose.

The Deep-Submicron Crisis and Physical Synthesis (Late 1990s – 2000s)

As process geometries shrunk below 0.25 microns (deep-submicron), the simplifying assumptions of the sequential synthesis-then-place-and-route flow broke down. Interconnect delay, rather than gate delay, became the dominant factor in circuit timing. This "interconnect crisis" necessitated another fundamental evolution:

• Physical synthesis: New tools blurred the line between logical and physical design. They performed placement-aware synthesis, using estimated wire lengths during logic optimization to produce netlists that were more likely to meet timing after detailed routing.
• Timing-driven design: The flow became dominated by timing constraints. Static timing analysis (STA) replaced gate-level simulation as the primary method for sign-off on timing performance.
• Design for Manufacturing (DFM): As features approached the wavelength of light used in lithography, geometric distortions became a critical issue. The flow incorporated DFM rules and techniques, such as optical proximity correction (OPC), to ensure the manufactured silicon matched the design intent. This era also saw the rise of intellectual property (IP) cores—pre-designed, reusable blocks like microprocessor cores, memory controllers, and interface protocols. Integrating these IP blocks became a standard part of the flow, moving design to a system-on-chip (SoC) paradigm.

The Modern Era: System-Level and High-Level Synthesis (2010s – Present)

Facing the challenges of designing billion-transistor chips and the rising costs of advanced process nodes, the contemporary ASIC flow continues to evolve upward in abstraction. The current frontiers include:

• Electronic System-Level (ESL) design: Tools and methodologies allow for architectural exploration, performance modeling, and virtual prototyping of entire systems using languages like SystemC and SystemVerilog, long before RTL is written.
• High-Level Synthesis (HLS): Building on the principles of early behavioral synthesis, modern HLS tools accept algorithmic descriptions in C, C++, or SystemC and automatically generate optimized RTL code, significantly raising designer productivity for complex data paths and signal processing blocks.
• Shift-Left in verification: Advanced verification methodologies, such as the Universal Verification Methodology (UVM), and widespread use of constrained-random testing and formal verification techniques are integrated earlier in the flow to catch bugs at the highest possible level of abstraction.
• Cloud-based EDA and AI/ML integration: The flow is increasingly supported by cloud computing infrastructure for scalable regression testing and massive parallel simulation. Furthermore, machine learning algorithms are being applied to areas like design space exploration, floorplanning, and analog circuit design to optimize outcomes that were previously intractable for purely algorithmic approaches. As noted earlier, the modern flow is characterized by a top-down, hierarchical approach. This structure has been solidified through decades of evolution, from its manual origins to the current era of system-level abstraction and intelligent automation, each stage driven by the need to manage the exponential growth in design complexity.

# Part templates for reuse

A critical methodology within the ASIC design flow involves the creation and systematic reuse of parameterized part templates. These templates, often implemented through specialized languages and libraries, abstract common circuit elements and design patterns into configurable, reusable components. This practice significantly enhances productivity, reduces errors, and ensures consistency across complex designs. The implementation of these templates spans various abstraction levels, from high-level behavioral descriptions to low-level physical netlists.

Hardware Description and Scripting Languages for Template Creation

The foundation for reusable part templates is built upon hardware description languages (HDLs) and specialized scripting libraries that extend general-purpose programming languages into the hardware domain. As noted earlier, HDLs like VHDL and Verilog are fundamental for designing digital components [5]. Beyond traditional HDLs, several frameworks enable template creation through more flexible, programmatic approaches. MyHDL is an open-source package that transforms Python into a hardware description and verification language [1]. It allows engineers to leverage the full Python ecosystem—including its extensive libraries and object-oriented capabilities—to create parameterized hardware models and testbenches [1]. This enables the development of highly configurable template libraries where circuit behavior, structure, and verification are all expressed in Python code, which can then be converted to standard Verilog or VHDL for synthesis. Similarly, SKiDL is a Python library specifically for designing electronic circuits, enabling the programmatic creation of netlists [16]. It allows designers to create parametric "smart" circuits that adapt based on requirements [16]. For instance, a template for a resistor divider can be defined with parameters for ratio, impedance, and power rating. A concrete implementation might involve creating component instances with specific values and physical footprints, as demonstrated by code to create two resistors with defined values and footprints [16]. This scriptable approach allows for the generation of variant circuits based on algorithmic calculations or external configuration files. SystemC, a set of C++ classes and macros, provides a framework for system-level modeling and serves as a platform for creating reusable transaction-level models (TLMs) [17]. The language is particularly suited to model system partitioning, to evaluate and verify the assignment of blocks to either hardware or software implementations, and to architect and measure interactions between functional blocks [17]. Template libraries in SystemC often consist of abstract channel models, bus functional models, and processor models that can be reconfigured for different system architectures.

Template Formats and Applications Across the Flow

Reusable part templates manifest in different formats tailored to specific stages of the ASIC design flow, from behavioral modeling to physical implementation. At the behavioral and architectural level, templates are often written in high-level languages like Python (with MyHDL), C++ (with SystemC), or specialized analog behavioral languages. These templates capture the intended function, performance constraints, and interface protocols of a block. For mixed-signal design, modeling techniques such as Digital Mixed Signal (DMS) technology are employed, which models analog signals using sampled data points to perform event-driven digital simulations [6]. This allows for the creation of reusable, fast-simulating behavioral models of analog blocks like phase-locked loops (PLLs) or data converters that can be integrated into digital testbenches early in the verification cycle. During logic synthesis and register-transfer level (RTL) design, templates are commonly instantiated as parameterized Verilog or VHDL modules. Parameters might include bus widths, FIFO depths, counter sizes, or state machine encoding styles. These RTL templates ensure consistent implementation of common structures like cross-clock domain synchronizers, arbiters, or error-correcting code (ECC) blocks across a project. Building on the concept of behavioral synthesis mentioned previously, high-level templates can be used to explore different micro-architectural implementations from the same functional specification. For physical design and layout, templates take the form of parameterized cells (P-cells) in tools like Cadence Virtuoso or as scripts for automated layout generation. The process of creating these physical templates, involving alternating stack deposition for layers, has been likened to making a layer cake and represents a significant initial challenge in the flow [3]. These P-cells define not only geometry but also design rule compliance and connectivity, allowing a single cell definition to generate correct layouts for transistors, capacitors, or resistors of any specified size. Furthermore, tools like the Electric VLSI Design System provide dialog controls for managing library name and path information that is written when generating a netlist, which is essential for maintaining consistent template integration across different design libraries [18].

Netlist and Integration Templates

At the netlist level, templates ensure consistent connectivity and integration of pre-designed blocks or intellectual property (IP). Circuit Description Language (CDL) is a netlist format used to describe electronic circuits at the transistor level and serves as a common template format for passing designs between schematic capture, simulation, and layout tools. A CDL template for a standard cell or a complex IP block defines the instance names, device parameters, and net connections in a portable text format. Integration templates also play a crucial role in verification setup. Modern debug systems, such as the Verdi Automated Debug System, simplify the process of co-simulation setup, which is vital when integrating templates from different abstraction levels (e.g., an RTL digital block with a transistor-level analog block) [4]. Verification IP (VIP) is itself a form of reusable template, providing pre-built, configurable components for standard interfaces like AMBA AXI, USB, or PCIe, which can be instantiated in testbenches to verify that a design template correctly implements a protocol. The management of these diverse templates—from Python SKiDL scripts and SystemC models to P-cells and CDL netlists—requires a robust design data management system. This system must track dependencies, parameters, versions, and ensure that the correct template variant is selected based on the target technology, performance corner, and project-specific configuration. The effective use of part templates for reuse transforms the ASIC design flow from a series of discrete, manual steps into a highly automated, repeatable, and scalable methodology for creating complex integrated circuits.

# Global power nets for multi-chip distribution

The distribution of power across multiple integrated circuits within a system presents a fundamental challenge in modern ASIC design, requiring specialized methodologies and tools to ensure reliable operation. As noted earlier, the breakdown of sequential synthesis-then-place-and-route flows in deep-submicron regimes necessitated new approaches to manage power integrity, which became a first-order constraint alongside timing closure [3]. Global power nets form the backbone of this distribution network, carrying supply voltages (VDD) and ground (GND) from external package pins to the internal circuitry of each chip, while managing the substantial currents and minimizing voltage drops (IR) and inductive noise (L di/dt) [1].

### Netlist Representation and Circuit Description Language

The physical implementation of power distribution networks begins with their representation in the design database. Circuit Description Language (CDL) serves as a critical netlist format for describing the topological connections of electronic circuits, including the hierarchical structure of power and ground nets [1]. Unlike simulation-focused formats, CDL provides a concise textual representation suitable for downstream physical implementation tools. A typical CDL entry for a power net might specify the net name, its connectivity to package pins and internal cell power ports, and its electrical properties. For example:

.NET VDD_GLOBAL
  PAD_VDD_1 PAD_VDD_2
  CELL_1:VDD CELL_2:VDD CELL_3:VDD
  + PROPERTY RESISTANCE_PER_SQ 0.05
  + PROPERTY WIDTH 10.0
.ENDNET

This declarative format allows floorplanning and routing tools to interpret the power network as a set of constraints before detailed physical design begins [1]. The specification of properties like sheet resistance and initial width provides initial targets for the power grid synthesis algorithms that follow.

### Power Grid Synthesis and Analysis Methodology

Following netlist definition, the creation of a robust power grid involves synthesis algorithms that determine the width, spacing, and layer assignment for the metal wires comprising the global nets. This process is analogous to building a layer cake, with alternating layers of orthogonal metal wires creating a mesh that covers the chip area [1]. The primary objectives are to meet target impedance (Z) specifications across a frequency spectrum and to limit static IR drop to typically 5-10% of the supply voltage. For a multi-chip system, the analysis extends to the package and board level, where the impedance of solder bumps, C4 bumps, or through-silicon vias (TSVs) must be incorporated. The effective impedance at a given location can be modeled as a combination of resistive (R), inductive (L), and capacitive (C) elements: Z(f) = R + j(2πfL - 1/(2πfC)) [1]. Synthesis tools use this model to iteratively adjust the grid, adding or widening wires until simulations predict that voltage fluctuations at the transistors remain within safe operating margins.

### Integration with Behavioral and RTL Design Flows

The planning for global power nets must be integrated early into the design flow, as choices made at the architectural and behavioral levels have profound impacts on power distribution requirements. MyHDL, an open-source package built on Python, enables this early integration by turning Python into a hardware description and verification language [2]. Engineers can use MyHDL to create executable specifications that include power intent, such as modeling the activity factors of different modules or estimating peak current demands. For instance, a designer might write a Python function using MyHDL decorators to describe a processor core, then use Python's scientific computing libraries to perform a preliminary analysis of its power profile across different workloads. This allows for architectural exploration where power delivery network (PDN) constraints can influence decisions like module placement, clock gating strategy, or the number of power domains before committing to a specific RTL implementation [2]. The ability to leverage the broader Python ecosystem for data analysis and visualization provides a significant advantage in optimizing the PDN co-design.

### Multi-Chip and 3D-IC Considerations

In advanced packaging schemes like 2.5D interposers or 3D stacked ICs, global power nets take on additional complexity. Power must be delivered through a hierarchy of networks: on the printed circuit board (PCB), through the package substrate or interposer, and finally through the die-to-die connections into each chip's internal grid [1]. Each interface introduces parasitic resistance and inductance that can exacerbate dynamic voltage droop. Methodologies for these systems often employ a chip-last approach, where the power delivery architecture for the entire stack is designed concurrently. This requires tools capable of modeling the combined RLC network of the full system. Specific challenges include:

• Managing current return paths for signals that traverse multiple dies, ensuring they do not cause excessive ground bounce
• Allocating sufficient through-silicon via (TSV) or micro-bump resources for power delivery versus signal routing
• Performing thermal-aware power grid design, as the resistivity of metal wires increases with temperature (ρ(T) = ρ₀[1 + α(T - T₀)]), potentially creating hot spots that degrade performance [1]
• Verifying electromigration limits across disparate manufacturing processes for the different dies in the stack

### Verification and Sign-Off

The final verification of global power nets employs a combination of static and dynamic analysis tools to achieve sign-off confidence. While static timing analysis has replaced gate-level simulation for timing sign-off as mentioned previously, power integrity verification relies heavily on dynamic simulation using extracted parasitic data (in formats like SPEF or DSPF) [1]. These simulations apply current waveforms, derived from vectorless or vector-based activity, to the detailed RLC model of the power grid to check for violations. Key sign-off checks include:

• Static IR drop: Ensuring the voltage at any point in the grid does not fall below a specified threshold (e.g., 90% of VDD) under DC conditions
• Dynamic IR drop: Verifying that transient voltage droops during simultaneous switching events do not exceed safe limits, typically 5-15% of VDD depending on the technology node
• Electromigration: Confirming that the current density in every wire segment remains below the specified limit for the wire's material, width, and temperature, often governed by Black's equation for mean time to failure (MTTF) [1]
• Power grid robustness: Analyzing the grid's response to large, fast current steps to ensure stability and adequate decoupling capacitance

Successful completion of these analyses allows the global power nets to be finalized, forming a critical piece of the physical design that enables reliable, high-performance operation of the multi-chip system [1][2].

# First subcircuit (e.g., AND gate on chip 1)

The implementation of a first subcircuit, such as a fundamental AND gate on a specific chip, represents the initial concrete instantiation of a design concept into a physically realizable form. This stage bridges the abstract functional specification and the eventual physical layout, serving as a critical proof-of-concept for the chosen design methodology and tool flow. The process involves selecting appropriate description languages, verifying functionality at a low level, and establishing the foundational patterns for hierarchical integration.

Circuit Description and Netlist Formats

At this granular level, the circuit is typically captured in a netlist format, which provides a structural description of electronic components and their interconnections. One such format is the Circuit Description Language (CDL), a text-based netlist standard used to describe circuits for simulation, verification, and eventual fabrication [1]. A CDL file for a basic two-input AND gate would explicitly list the transistors (e.g., PMOS and NMOS devices), their instance names, the nodes (nets) to which their terminals (source, gate, drain, bulk) connect, and relevant device parameters such as width (W) and length (L). For example, a static CMOS AND gate might require six transistors: two PMOS devices in parallel for the pull-up network and four NMOS devices in series for the pull-down network. The CDL netlist defines this topology without ambiguity, enabling tools to perform circuit simulation (SPICE) or translate the description into a layout [1]. This low-level representation is essential for analyzing performance characteristics like:

• Propagation delay (tpd), calculated from the RC time constants of the transistor networks and interconnect
• Power consumption, comprising static leakage current (I_leak) and dynamic switching power (C_LV_DD²f)
• Noise margins, which determine the gate's robustness to voltage fluctuations on its inputs

High-Level Abstraction with MyHDL

In contrast to structural netlists, higher-level abstraction can accelerate the design and verification of even basic blocks. MyHDL is an open-source package that leverages the Python programming language as a hardware description and verification language (HDVL) [2]. It allows engineers to describe hardware behavior using Python's syntax and constructs, such as generators to model concurrent processes and decorators like @always to describe combinatorial or sequential logic. For the AND gate example, a designer could write a MyHDL model that defines the Boolean function (z = a & b) and then use Python's extensive ecosystem for simulation, testing, and data analysis [2]. A key feature is MyHDL's ability to convert these Python-based models into synthesizable Verilog or VHDL code, as well as into verification stimuli for downstream simulation tools. This enables a workflow where the gate's function is validated within a powerful software environment before committing to a specific gate-level implementation. The process of transforming a high-level Python description into a gate-level netlist and eventually a physical layout is analogous to constructing a layered cake, where each stage adds a new level of definition and constraint, with this initial subcircuit definition representing the first major deposition in that flow-alternating stack [2].

Verification and Characterization

Once a netlist or high-level model is created, the subcircuit undergoes rigorous verification. This involves several analyses to ensure it will function correctly within the larger system context. Building on the methodology mentioned previously, static timing analysis (STA) would be applied at this microscopic scale to check setup and hold times for any sequential elements (like a latched version of the gate) and to calculate min/max path delays [4]. Furthermore, power integrity analysis becomes relevant, even for a single gate, as it must be designed to meet the primary objectives of limiting static IR drop to acceptable levels (typically 5-10% of V_DD) and presenting a suitable impedance profile to the power network to prevent dynamic voltage droops [5]. Simulation at the transistor level (SPICE) provides the most accurate characterization of switching waveforms, output drive strength, and sensitivity to process variations (e.g., corner analysis for fast-fast, slow-slow, and typical transistor models). The results of these analyses, such as a propagation delay of 15 ps under typical conditions or a leakage current of 1 nA, become the foundational data points for the cell library used in automated synthesis of larger blocks.

Integration into the Hierarchical Flow

The finalized and characterized subcircuit does not exist in isolation. It becomes a leaf cell in the hierarchical design approach noted earlier. Its netlist description (e.g., in CDL) or behavioral model (e.g., from MyHDL conversion) is stored in a library. When a higher-level module, such as an adder or a finite state machine, is synthesized, the logic synthesis tool selects instances of this AND gate from the library to implement the required logic function. The physical design of the gate—its layout—is also created, defining the precise geometric shapes on different semiconductor layers (diffusion, polysilicon, metal) that form the transistors and wires. This layout must obey all design rules (DRC) for the target technology node. The abstracted view of this layout, containing timing, power, and connectivity information, is called a standard cell. The creation and validation of this first subcircuit cell establishes a template and validates the entire tool chain for the subsequent, more complex stages of the design flow, where millions of such instances will be placed, routed, and optimized to create the final integrated circuit.

# Second subcircuit (reuse on chip 2)

The second subcircuit, designated for reuse on a subsequent integrated circuit (chip 2), represents a critical methodology for improving design productivity and ensuring consistency across product generations. This approach leverages previously verified circuit blocks, encapsulating them as intellectual property (IP) cores to be instantiated within new designs. The process involves specific description formats, specialized design languages, and a layered verification strategy that mirrors the complexity of modern semiconductor manufacturing.

### Circuit Description Language (CDL) for Netlist Representation

For the physical reuse of a digital subcircuit, a precise, technology-independent netlist description is essential. The Circuit Description Language (CDL) serves this purpose as a textual netlist format used to describe electronic circuits at the transistor or gate level [1]. Unlike behavioral or register-transfer level (RTL) descriptions, CDL provides a structural representation of the circuit's components and their interconnections, which is crucial for downstream physical implementation tools. A typical CDL file for a reusable block includes:

• A header defining the subcircuit name and its input/output ports
• Instance statements for each transistor or standard cell, specifying the component type and its connections to nets
• Parameter definitions for device sizes (e.g., W/L ratios for MOSFETs)
• Subcircuit calls for hierarchical designs, allowing complex blocks to reference other CDL-defined blocks

For example, the CDL entry for a two-input NAND gate might specify the PMOS and NMOS transistors, their drain, gate, and source connections, and the geometric dimensions critical for performance and power characteristics [1]. This low-level description becomes the golden reference for layout versus schematic (LVS) checking and is a mandatory deliverable for any reusable IP block intended for fabrication.

### High-Level Design and Verification with MyHDL

While CDL handles the structural netlist, the functional design and verification of the reusable subcircuit often begin at a higher abstraction level. MyHDL is an open-source, pure Python package that enables this process by turning Python into a hardware description and verification language [2]. It provides hardware engineers with the power of the Python ecosystem—including its extensive libraries for numerical computation, data analysis, and test automation—within a hardware design context [2]. MyHDL allows designers to:

• Write executable specifications for digital circuits using Python generators, which model concurrent processes
• Create cycle-accurate or transaction-level models for simulation and verification
• Automatically generate Verilog or VHDL code for synthesis, bridging the gap between high-level algorithm development and RTL implementation
• Develop sophisticated testbenches using Python's unit testing frameworks and assertion libraries

A key application of MyHDL in subcircuit reuse is the creation of a "reference model" of the block's intended behavior. This Python model can be co-simulated against the RTL description (often generated from the MyHDL code itself) and the eventual gate-level netlist to ensure functional consistency across all stages of the design flow [2]. This multi-abstraction verification is vital for certifying a block as reusable IP.

### Behavioral Synthesis and the Layered Design Process

The transformation from a high-level algorithmic description in a language like Python (via MyHDL) to a register-transfer level (RTL) description is the domain of behavioral synthesis. This process, which is like making a layer cake, represents the first big challenge in the flow-alternating stack deposition of design abstractions [3]. Behavioral synthesis tools analyze an untimed or partially timed algorithmic model and perform several automated steps:

• Scheduling: Assigning operations to specific clock cycles
• Allocation: Determining the number and type of hardware resources (e.g., adders, multipliers) required
• Binding: Mapping variables and operations to specific registers and functional units

The output is a cycle-accurate RTL description in a language like Verilog or VHDL, which is then suitable for logic synthesis. For a reusable subcircuit, this synthesized RTL, along with its constraints (timing, area, power), becomes a core deliverable. The process ensures that the block's architecture is optimized not just for function, but for the target performance and technology parameters, making it a robust candidate for reuse [3].

### Integration and Verification in the IEEE Context

The development and qualification of reusable subcircuits occur within a framework of established engineering standards and practices. The IEEE Xplore digital library serves as a primary repository for research on design methodologies, verification techniques, and case studies relevant to IP reuse [4]. Furthermore, the integration of a pre-designed subcircuit into a new chip (chip 2) necessitates rigorous interface verification. This includes:

• Protocol Checking: Ensuring the block's communication interfaces (e.g., AXI, AHB, proprietary buses) comply with relevant specifications.
• Clock Domain Crossing (CDC) Analysis: Verifying proper synchronization for signals traversing between the reused block's clock domain and the new chip's clock domains.
• Power Intent Validation: Confirming that the block's power switches, isolation cells, and level shifters are correctly integrated into the new chip's Unified Power Format (UPF) or Common Power Format (CPF) power plan. Building on the concept discussed earlier where static timing analysis (STA) replaced gate-level simulation for sign-off, the reused block must be delivered with its own Liberty (.lib) timing models and characterized for all required PVT (Process, Voltage, Temperature) corners. This enables chip-level STA to verify that integrating the block does not violate timing constraints in the new context [4]. The successful reuse of a subcircuit thus depends on a complete package of deliverables—CDL netlist, synthesized RTL, verification testbenches, timing models, and integration guidelines—all developed and validated through this multi-layered, tool-assisted flow.

# Board-level power

Board-level power design and analysis constitute a critical phase in the ASIC design flow, focusing on the integrity and efficiency of the power delivery network (PDN) from the system board to the integrated circuit itself. This stage ensures that the ASIC receives clean, stable power across all operational modes, which is fundamental for achieving target performance, reliability, and signal integrity. Failure to adequately design the board-level PDN can lead to timing violations, logic errors, excessive electromagnetic interference (EMI), and reduced product lifetime.

### Power Delivery Network (PDN) Architecture and Components

The board-level PDN is a hierarchical network of passive components and copper planes designed to source current from the voltage regulator module (VRM) to the ASIC's power pins. Its architecture must manage current demands that can switch from milliamps to tens of amps within nanoseconds in modern high-performance designs. The key components include:

• Voltage Regulator Modules (VRMs): These switch-mode power supplies convert the board's input voltage (e.g., 12V) to the required core and I/O voltages (e.g., 0.8V, 1.2V). Their bandwidth, typically limited to a few hundred kHz, defines the low-frequency impedance profile [2].
• Bulk Capacitors: Electrolytic or tantalum capacitors with high capacitance (10s to 1000s of µF) are placed near the VRM to handle low-frequency current transients and stabilize the DC supply [2].
• Ceramic Decoupling Capacitors: A distributed array of multilayer ceramic capacitors (MLCCs), ranging from 100nF to 10µF, are placed on the board near the ASIC package. These manage mid-frequency impedance (from ~100 kHz to 10-50 MHz) by providing localized charge reservoirs [2].
• Power and Ground Planes: Adjacent copper layers in the printed circuit board (PCB) form a parallel-plate capacitor, providing inherent high-frequency decoupling (from 10s of MHz to 1+ GHz) with very low parasitic inductance. The plane capacitance is given by C = ε₀εᵣ * A / d, where A is the overlapping area and d is the dielectric separation [2].
• Package Parasitics: The bond wires, leads, and internal package traces contribute series resistance (R_pkg) and inductance (L_pkg), which become significant bottlenecks at high frequencies, often above 100 MHz [2]. The combined impedance of this network, as seen from the ASIC's silicon die, must remain below a target impedance (Z_target) across the entire frequency range of interest, from DC to the highest harmonic of the switching current. Z_target is calculated as Z_target = Vdd * Ripple_allowed / ΔI, where Vdd is the supply voltage, ΔI is the maximum current step, and Ripple_allowed is the permissible voltage deviation (often 3-5%) [2].

### Analysis Methodologies and Simulation

Analyzing the PDN requires a multi-faceted simulation approach to model its behavior from DC to gigahertz frequencies. As noted earlier, static timing analysis (STA) replaced gate-level simulation for timing sign-off, but for power integrity, specialized analyses are employed.

• DC Analysis (IR Drop): This analysis calculates the static voltage drop from the VRM to each power pin on the ASIC package due to the resistance of PCB traces, planes, and vias. Tools solve the resistive network using modified nodal analysis to ensure the voltage at the pin meets the minimum required by the ASIC after accounting for drop. Limits are typically 5-10% of Vdd [1].
• AC Analysis (Impedance Profile): The frequency-domain impedance (Z(f)) looking into the PDN from the ASIC is the most critical metric. It is simulated using SPICE or specialized power integrity tools that model all network parasitics (R, L, C of all components and interconnects). The goal is a flat, low-impedance profile where the VRM, bulk capacitors, ceramic capacitors, and plane capacitance each dominate and suppress impedance peaks in their respective frequency bands [2].
• Transient Analysis: This time-domain analysis simulates the PDN's response to actual current waveforms drawn by the ASIC, often represented as current sources (I(t)) in simulation. It verifies that voltage transients (droop and overshoot) during sudden current changes remain within specification [2].

### Design Challenges and Mitigation Techniques

The move to deep-submicron technologies, where, as previously covered, simplifying assumptions broke down below 0.25 microns, intensified board-level power challenges. Higher clock frequencies, lower supply voltages, and increased current densities make power integrity harder to achieve.

• Simultaneous Switching Noise (SSN): Also called ground bounce or ΔI-noise, this occurs when many I/O buffers switch simultaneously, causing a large, fast current surge through the package inductance (L_pkg * dI/dt). This can corrupt power rails and cause false switching in quiet I/O cells. Mitigation involves using low-inductance packages (like flip-chip), increasing the number of power/ground pins, and implementing staggered I/O switching [2].
• Resonance and Anti-Resonance: The interaction between the inductance of capacitors and their capacitance, as well as plane cavity resonances, can create sharp impedance peaks (anti-resonances) at specific frequencies. These peaks can amplify noise. Mitigation requires careful selection of capacitor values to spread resonances and the use of embedded planar capacitance materials [2].
• High-Frequency Decoupling: At frequencies beyond 500 MHz, the effectiveness of discrete capacitors diminishes due to their inherent equivalent series inductance (ESL). The primary decoupling mechanism becomes the PCB's power-ground plane capacitance. Minimizing the dielectric thickness (d) between planes maximizes this intrinsic capacitance [2].
• Multi-Domain Power Management: Modern ASICs have dozens of power domains for different cores, memories, and analog blocks. The board-level PDN must support complex power-up/power-down sequences, isolation, and retention voltages, requiring precise coordination between the ASIC's internal controllers and board-level power sequencers.

### Integration with Chip-Level and System-Level Analysis

Board-level power analysis does not occur in isolation. It requires models and data from both the ASIC design and the broader system. The ASIC design team must provide accurate current consumption profiles, including:

• Static (Leakage) Current: A DC value.
• Time-Based Current Waveforms (IBIS-AMI or VCD-based): Dynamic current drawn over a representative workload cycle.
• Package Model: A detailed electrical model (often an S-parameter or SPICE netlist) of the package's power distribution. These models are integrated into the board-level simulation to perform a co-analysis. Furthermore, the board-level PDN impedance profile is often provided back to the chip-level design team for use in on-chip power grid analysis, creating a closed-loop verification process to ensure robustness at the system level [2]. In summary, board-level power design is a discipline of impedance control, requiring careful component selection, strategic placement, and comprehensive multi-domain simulation to build a PDN that can support the demanding electrical needs of modern ASICs. Its success is foundational to the stability and performance of the final silicon product.

# Part templates for reuse

A critical methodology for improving productivity and reducing time-to-market in ASIC design is the systematic reuse of pre-designed and pre-verified functional blocks, known as intellectual property (IP) cores or part templates. This practice moves beyond the ad-hoc copying of previous designs to establish a structured, library-based approach where complex functions are encapsulated as reusable components with well-defined interfaces, documentation, and verification suites.

Standardized Description Formats and Libraries

The foundation of effective IP reuse is the use of standardized description formats that allow a design block to be integrated into various tool flows and target technologies. While hardware description languages (HDLs) like VHDL and Verilog are common, other specialized formats exist for different stages of the flow. The Circuit Description Language (CDL) is a netlist format used to describe electronic circuits at the transistor level, often serving as an intermediate representation between schematic capture and layout, or as a deliverable for hard IP macros [1]. For soft IP, which is synthesized for each target technology, providers often deliver packages containing:

• Synthesizable RTL code in Verilog or VHDL
• Comprehensive testbenches and verification IP (VIP)
• Constraint files (SDC) for timing and power
• Technology-independent netlists (e.g., in EDIF format)
• Detailed datasheets with timing models, power estimates, and integration guides

The creation of these reusable blocks is supported by high-level synthesis (HLS) tools and methodologies, which allow designers to capture functionality at an algorithmic level using C, C++, or SystemC before automatically generating optimized RTL. Cadence's knowledge base details methodologies where behavioral synthesis transforms algorithmic descriptions into register-transfer level implementations, enabling the creation of parameterizable IP cores [2].

Open-Source Frameworks and Ecosystem Integration

The rise of open-source hardware design tools has introduced new paradigms for creating and sharing reusable templates. MyHDL is an open-source, pure Python package that turns Python into a hardware description and verification language, providing hardware engineers with the power of the Python ecosystem [1]. By using Python decorators and generators, MyHDL allows designers to write executable specifications that can be simulated, converted to Verilog or VHDL for synthesis, and used to create reusable, parameterizable components. This approach leverages Python's extensive libraries for verification, data analysis, and automation, creating a powerful environment for IP development. A typical MyHDL-based IP block includes:

• A Python module defining the hardware structure and behavior
• A built-in self-checking testbench using Python's unittest or pytest frameworks
• Conversion scripts to generate synthesizable Verilog/VHDL
• Configuration files for different parameterizations (e.g., data width, pipeline depth)

Integration and Verification Challenges

Successfully integrating third-party IP into a larger ASIC design presents significant technical challenges that reuse methodologies must address. The primary concerns include:

• Interface Compatibility: Ensuring the IP's communication protocols (AMBA AXI, AHB, APB, OCP, etc.) match the system interconnect
• Clock Domain Crossing (CDC): Properly synchronizing signals between IP cores operating in different clock domains
• Power Domain Integration: Configuring power switches, isolation cells, and level shifters for IP in multiple voltage domains
• Test Integration: Incorporating the IP into the chip's overall DFT (Design for Test) strategy, including scan chains and memory BIST

To mitigate these challenges, IP providers deliver verification IP (VIP) that models bus protocols and checks compliance, along with Unified Power Format (UPF) or Common Power Format (CPF) files describing power intent. The quality of reusable IP is often certified against standards like the IEEE 1685-2014 (IP-XACT) standard, which defines an XML schema for describing and packaging IP components to enable automation in tools from different vendors [3].

Economic and Organizational Models

The business of IP reuse operates through several distinct models, each with different trade-offs between cost, risk, and control:

• Internal Reuse: Development and sharing of IP within a single company or design group, offering maximum control but requiring internal infrastructure and management
• Commercial Licensing: Procurement of IP from specialized vendors (e.g., Arm, Synopsys, Cadence), providing proven, verified components with professional support but at significant licensing cost
• Open-Source Cores: Utilization of freely available IP from communities like OpenCores, CHIPS Alliance, or RISC-V, offering zero licensing cost but variable quality and limited support
• Foundry IP: Technology-specific libraries (standard cells, I/Os, memory compilers) and analog IP (PLLs, SerDes) provided directly by semiconductor foundries, essential for physical implementation

Research indicates that successful IP reuse programs require not only technical infrastructure but also organizational processes including catalog management, version control, quality metrics, and legal frameworks for licensing and liability [3]. The return on investment comes from amortizing the high initial development and verification cost of an IP block across multiple projects, potentially reducing design effort for complex functions by 70-80% compared to ground-up development.

Future Directions and Standardization

The evolution of part template reuse continues with several emerging trends. The increasing adoption of the RISC-V instruction set architecture has spurred development of a vibrant ecosystem of open-source processor cores and peripherals. Chiplets—small, pre-manufactured die that are integrated into advanced packages using technologies like silicon interposers—represent a physical manifestation of IP reuse at the silicon level. Additionally, machine learning techniques are being applied to recommend IP components based on design requirements and to automatically generate integration code. Ongoing standardization efforts through organizations like Accellera and the IEEE aim to improve interoperability through specifications for portable stimulus, verification metadata, and security annotation for IP blocks [3].

# Global power nets for multi-chip distribution

The design of global power distribution networks (PDNs) for multi-chip systems represents a critical and complex challenge in modern ASIC design flows, particularly for advanced packaging technologies like 2.5D and 3D integration. This task extends beyond the power integrity concerns of a single die to encompass the coordinated delivery of stable, low-noise power supplies across multiple heterogeneous chiplets or dies within a single package or module. The objective is to create a robust, low-impedance path from the system-level voltage regulator modules (VRMs) to the active transistors on every chip, managing current demands that can exceed hundreds of amperes with nanosecond-scale transients [1].

### Network Architecture and Hierarchical Decoupling

A hierarchical strategy is essential for managing impedance across the broad frequency spectrum inherent in multi-chip operation. This hierarchy is typically segmented into three primary domains:

• System-Level Distribution: This encompasses the PCB-level power planes and traces that deliver power from the VRM to the package. Target impedance at this level is often in the single-digit milliohm range to handle the aggregate current of all chips [1].
• Package-Level Distribution: Within the package substrate or interposer, a dedicated power delivery network (PDN) routes power to each chiplet. This layer must manage current redistribution between chips and provide mid-frequency decoupling. Technologies like silicon interposers with through-silicon vias (TSVs) enable dense power grid structures with lower parasitic inductance compared to organic substrates [2].
• Chip-Level Distribution: As noted earlier, each chip has its internal PDN, comprising global grids, intermediate layers, and local cell-level connections. In a multi-chip context, the design of each chip's PDN must be co-optimized with the package-level network to which it connects. The decoupling strategy follows this hierarchy. Bulk capacitors on the PCB address low-frequency noise. Mid-frequency decoupling, as previously mentioned, is provided by package-mounted capacitors. High-frequency decoupling relies on the intrinsic capacitance of the package's power-ground planes and the on-die capacitance of the chips themselves [1]. The integration of deep-trench capacitors or metal-insulator-metal (MIM) capacitors within the chip or interposer is a key technology for enhancing high-frequency performance in multi-chip modules [2].

### Modeling and Analysis Challenges

Accurate modeling of a multi-chip PDN requires a unified approach that combines models from different physical domains and abstraction levels. The overall network is an interconnected mesh of resistive, inductive, and capacitive (RLC) elements.

• Chip PDN Models: These are typically extracted as detailed RLC networks from the chip's physical layout, representing the metal layers and vias.
• Package/Interposer Models: These are generated from the package substrate design, often using 2.5D or 3D electromagnetic (EM) field solvers to capture the frequency-dependent behavior of planes, traces, and TSVs [2].
• PCB and VRM Models: These include the PCB plane models and the impedance profile of the voltage regulators. The chip, package, and board models are connected at their interfaces (e.g., C4 bumps, micro-bumps) to form a complete system model. Analyzing this model involves simulating the impedance profile, $Z(f)$, looking from the terminals of each chip's active circuitry back through the network. The target impedance, $Z_{target}$, for the system is calculated based on the most demanding chip's requirements, using the formula $Z_{target} = V_{dd} \times Ripple_{allowed} / \Delta I$, where the parameters are defined for the worst-case current transient ($\Delta I$) among all chips [1]. A critical analysis is the simulation of simultaneous switching noise (SSN), also known as ground bounce or $\Delta I$-noise. When multiple drivers across different chips switch simultaneously, the large, fast current draw through the PDN's inductance causes voltage droops and spikes. System-level simulation tools are used to inject current profiles from the activity of all chips into the unified PDN model to verify that voltage rails at each chip remain within specified limits [2].

### Design Methodologies and Co-optimization

Given the interdependencies, a sequential design flow where chips and package are designed independently is insufficient. A co-design methodology is necessary:

1. Early Planning and Budgeting: Power budgets (average and peak current) are allocated to each chiplet. Initial target impedances are set for the system, package, and individual chip PDNs based on these budgets and the overall ripple allowance [1]. 2. Architectural Exploration: Different package PDN topologies (e.g., power mesh design in an interposer, placement of package decoupling capacitors) are evaluated using early, approximate models of the chiplets to find a feasible solution space [2]. 3. Iterative Refinement: As chip designs mature, their detailed PDN models are integrated with the package model. Iterative analysis identifies hotspots—chips or regions where impedance targets are violated. Mitigation may involve:

• Redistributing on-chip decoupling capacitance. - Modifying the package PDN layout (e.g., adding more power/ground TSVs, thickening planes). - Adjusting the chip's physical design (e.g., adding more power straps). 4. Sign-off Verification: The final sign-off involves a full-system PDN analysis with extracted parasitics from all final layouts (chips and package), verifying voltage integrity under a comprehensive set of workload-driven current scenarios [2].

### Impact of Advanced Packaging

Advanced packaging technologies directly influence global PDN design. A 2.5D system with a silicon interposer offers a superior PDN compared to a traditional organic package substrate. The interposer's fine-pitch TSVs and ability to fabricate high-density metal layers allow for a very low-inductance, mesh-like power distribution network directly beneath the chiplets [2]. In 3D stacked ICs, where dies are bonded face-to-face, through-silicon vias (TSVs) provide vertical power delivery. However, this introduces new challenges in managing current density in TSVs and thermal gradients that affect wire resistance [2]. In both cases, the power delivery for the entire stack must be planned holistically, as the topmost die in a 3D stack relies on the PDNs of the dies beneath it.

### Verification and Sign-off

Final verification of the global power nets requires a confluence of analyses:

• DC IR Drop Analysis: Ensures that the static voltage drop from the VRM to the transistors on every chip does not exceed specified limits, typically 5-10% of Vdd as noted previously, across all operational corners (process, voltage, temperature).
• AC/Transient Analysis: Simulates dynamic voltage droop and overshoot caused by current transients from all chips operating concurrently, using extensive vector-based or statistical activity patterns.
• Electromigration (EM) Analysis: Checks that current densities in all network segments (on-chip, in TSVs, in package traces) remain below reliability thresholds to prevent premature failure. Successful design of global power nets for multi-chip distribution is a cornerstone for realizing the performance and integration benefits of chiplet-based systems. It demands tight collaboration between chip, package, and system designers, supported by advanced modeling tools and co-design methodologies that treat the power delivery system as a single, critical entity spanning multiple silicon dies and packaging layers [1][2].

# First subcircuit (e.g., AND gate on chip 1)

The creation of a first subcircuit, such as a fundamental AND gate destined for integration onto a specific chip, represents the initial concrete implementation step in the ASIC design flow. This stage transitions from abstract system-level planning and architectural definition to the creation of a specific, synthesizable hardware description that will ultimately become physical silicon. The process involves selecting appropriate description languages, implementing the logic, and preparing the design for integration into the larger hierarchical system [1].

Hardware Description and Implementation Languages

The implementation of a basic digital subcircuit typically begins with its description in a hardware description language (HDL). While VHDL and Verilog remain industry standards for register-transfer level (RTL) design, alternative approaches and formats exist for specific purposes. Circuit Description Language (CDL) is one such netlist format, used to describe electronic circuits at the transistor or gate level, often for simulation, verification, or as an intermediate representation between higher-level HDL and final layout [1]. It provides a textual means to define connectivity, component instances, and their parameters. In parallel, the landscape of design entry has expanded with high-productivity languages. MyHDL transforms Python into a hardware description and verification language by providing constructs to model concurrency, signals, and hardware-oriented data types, thereby granting hardware engineers access to the extensive Python ecosystem for tasks like test generation, data analysis, and functional verification [2]. This approach allows for a more agile and software-like methodology in the early stages of creating and verifying subcircuit blocks.

The Synthesis and Abstraction Stack

The journey from a Boolean equation or truth table (e.g., for a two-input AND gate: Z = A · B) to a placed-and-routed instance on a die involves navigating a stack of design abstractions. As noted earlier, this process is akin to building a layer cake and presents a primary challenge in the flow [3]. For the first subcircuit, this begins with behavioral or RTL description. The designer must create a model that is not only functionally correct but also suitable for logic synthesis—the automated process that translates the HDL into a gate-level netlist composed of cells from a specific vendor's standard cell library. This synthesis step imposes critical decisions and constraints on the subcircuit design:

• Area vs. Speed: The designer can direct the synthesis tool to optimize for minimum silicon area or maximum operating speed. For a simple gate, this might involve choosing between a smaller, slower standard cell implementation or a larger, faster one with higher drive strength.
• Fan-out and Loading: The output of the subcircuit must be designed to drive its estimated capacitive load, which includes the input capacitance of all gates it connects to (its fan-out) plus the parasitic wiring capacitance. Failure to account for this leads to excessive signal propagation delay.
• Testability: From the outset, the subcircuit structure should facilitate automated test pattern generation (ATPG) for manufacturing defects. This often entails incorporating scan flip-flops or ensuring certain controllability and observability rules are followed. Following RTL synthesis, the gate-level netlist undergoes physical implementation. Building on the concepts discussed above, automation handles placement and routing, but timing closure becomes paramount [4]. For the individual subcircuit, this means its internal timing paths must meet setup and hold time requirements relative to the clock signals it uses. Static timing analysis (STA) is run on the gate-level model to verify this, considering the estimated interconnect delays from initial placement [5]. Any violations must be corrected by modifying the RTL, applying synthesis constraints, or later during physical optimization.

Integration into the Hierarchical Flow

The first subcircuit is rarely designed in isolation. It is a leaf cell in a much larger hierarchical design. Therefore, its design interface must be meticulously defined to ensure seamless integration:

• Interface Protocol Compliance: The subcircuit's input and output signals must adhere to the timing and electrical specifications of the on-chip bus or protocol it interfaces with (e.g., synchronous handshaking, specific setup/hold times).
• Power and Ground Connectivity: The subcircuit must be designed with power (VDD) and ground (GND) pins that will connect to the global power distribution network (PDN). Its internal power consumption and switching current profiles contribute to the chip's overall power budget and IR drop analysis.
• Clock and Reset Distribution: The subcircuit must properly integrate with the global clock tree and reset network, presenting a defined clock load and respecting reset recovery/removal times.

Verification and Validation

Before the subcircuit is committed to the full chip integration, it undergoes rigorous verification. This typically involves:

• Unit-Level Simulation: The subcircuit's HDL model is simulated in isolation with a comprehensive testbench to verify its functionality against its specification across all corner cases.
• Formal Verification: For critical control logic, formal property checking may be used to mathematically prove the subcircuit behaves correctly under all possible input sequences.
• Equivalence Checking: After synthesis, the gate-level netlist is formally compared to the original RTL to ensure the translation process introduced no functional errors. The successful design, implementation, and verification of this first subcircuit establishes a template and quality standard for all subsequent blocks in the ASIC. It validates the chosen tool flow, library models, and design methodology, paving the way for the incremental construction of the complete system-on-chip.

# Second subcircuit (reuse on chip 2)

The design and integration of a second subcircuit intended for reuse on a subsequent chip (Chip 2) represents a distinct phase in the ASIC design flow, shifting focus from initial creation to systematic intellectual property (IP) adaptation. This process leverages the foundational work completed for the first subcircuit but introduces unique challenges centered on portability, verification, and integration into a new system context. The primary goal is to transform a proven circuit block into a reusable, well-documented IP component that can be efficiently deployed with predictable results, thereby amortizing non-recurring engineering (NRE) costs across multiple projects [1].

Foundational Formats and the Role of CDL

A critical enabler for IP reuse is the use of standardized, technology-agnostic description formats. Unlike proprietary or tool-specific formats, CDL provides a portable textual representation of a circuit's components—transistors, resistors, capacitors—and their interconnections. For a reusable subcircuit, generating a clean, well-commented CDL netlist is a crucial deliverable. This netlist acts as a golden reference model that can be read by various simulation, verification, and physical implementation tools across different design environments, ensuring the core functionality of the IP is preserved independent of downstream processing [1].

Modern High-Level Design and MyHDL

While CDL operates at a low level of abstraction, the creation and verification of reusable subcircuits increasingly begin at higher abstraction levels to improve productivity and correctness. It provides hardware engineers with access to the extensive Python ecosystem, including its powerful libraries for testing, data analysis, and automation [2]. For a second subcircuit, MyHDL can be used to create a parameterizable, high-level model of the IP. This model serves multiple reuse purposes:

• Architectural Exploration: Quickly evaluating different microarchitectures or bit-widths for the new target application on Chip 2.
• Functional Golden Reference: Generating a cycle-accurate or transaction-level model against which lower-level implementations (RTL, gate-level netlist) can be verified.
• Automated Test Generation: Using Python's frameworks to create comprehensive, self-checking testbenches that travel with the IP. The transition from a high-level MyHDL model to a synthesizable register-transfer level (RTL) description and finally to a gate-level CDL netlist embodies the hierarchical, abstraction-layered nature of the design flow.

Verification and Validation for Reuse

Verification of a reusable subcircuit is substantially more rigorous than for a block designed for a single-use ASIC. The IP must be validated not only for its intended function but also for correct operation across a wider range of parameters, process corners, and integration scenarios anticipated for future reuse. This involves:

• Extended Regression Testing: A comprehensive suite of tests, potentially developed using MyHDL's verification capabilities, must be maintained and executed against any modification of the IP [2].
• Protocol and Interface Compliance: The IP's communication interfaces (e.g., AMBA AXI, AHB, APB) must be rigorously verified for compliance with relevant specifications to ensure plug-and-play compatibility in different System-on-Chip (SoC) environments [1].
• Formal Verification: Applying formal property checking to prove the correctness of critical control logic and interface protocols under all possible input conditions, providing a level of assurance beyond simulation. Research on advanced verification methodologies and case studies for complex IP reuse is extensively documented in repositories like the IEEE Xplore digital library [1].

Physical Design and Portability Considerations

The physical implementation of the reusable subcircuit must be planned for portability. This often involves the creation of a "hard macro"—a fully placed, routed, and timing-closed physical layout of the block. Key considerations include:

• Technology Independence: While the final macro is built for a specific semiconductor process, the RTL and synthesis scripts should be written to be as technology-agnostic as possible, using process-independent cell libraries and timing constraints.
• Abstract Models: For the integrator of Chip 2, the hard macro is accompanied by abstract models, including:
• LEF (Library Exchange Format): Defines the macro's physical outline, pin locations, and blockages.
• Timing Library (.lib): Provides detailed delay, power, and noise characteristics for static timing analysis.
• CDL Netlist: For transistor-level simulation and formal equivalence checking.
• Power and Signal Integrity: A robust power distribution network (PDN) within the macro is essential. Building on concepts discussed above, the macro must be designed to meet target impedance specifications internally. Furthermore, it must include a sufficient number of power and ground pads/rings and provide clear guidelines for connecting to the chip-level PDN, including recommendations for local decoupling capacitance [1].

Integration into the New System Context

Finally, the subcircuit is integrated into the design of Chip 2. This integration phase presents its own challenges:

• Context-Specific Configuration: The IP's parameters (e.g., data bus width, buffer depth) are set for the new application.
• System-Level Verification: The IP is verified within the full context of Chip 2, including interactions with new neighboring blocks, the system memory map, and shared resources.
• Physical Integration: The hard macro is placed within the Chip 2 floorplan, and its power, clock, and signal networks are connected to the top-level chip routes. Special attention is paid to interface timing, as the physical proximity of the macro to other blocks on Chip 2 will differ from its location on the original chip. The successful reuse of a second subcircuit validates the investment in creating a high-quality, well-documented IP block. It demonstrates a mature design flow capable of managing complexity through abstraction, automation, and standardization, ultimately reducing risk and time-to-market for subsequent ASIC projects [1][2].

# Board-level power

Board-level power integrity is a critical subsystem within the ASIC design flow, focused on ensuring stable and clean power delivery from the printed circuit board (PCB) to the integrated circuit's package and ultimately its silicon die. This discipline has grown in complexity with technology scaling, where the transition to deep-submicron processes intensified board-level power challenges due to higher current densities, faster switching speeds, and lower supply voltages [12]. Effective power integrity design prevents logic errors, reduces electromagnetic interference (EMI), and ensures long-term reliability by mitigating voltage noise that can degrade performance.

### Power Distribution Network (PDN) Modeling and Target Impedance

The design of the board-level Power Distribution Network (PDN) begins with modeling it as a network of parasitic resistances (R), inductances (L), and capacitances (C) between the voltage regulator module (VRM) and the ASIC's power pins. The target impedance, Z_target, is the maximum allowable PDN impedance across the relevant frequency range to maintain voltage within specified ripple limits. For a modern ASIC with a 1.0V core supply, a 5% ripple allowance (50 mV), and a maximum current step of 10A, the target impedance would be 5 mΩ. The PDN design must ensure its impedance profile, derived from frequency-domain analysis, remains below this target value from DC up to the maximum frequency of concern, which can extend into the gigahertz range.

### Multi-Domain Decoupling Strategy

Achieving a low-impedance PDN requires a hierarchical decoupling strategy using capacitors of different technologies and values placed at various locations. This strategy addresses impedance across distinct frequency bands:

• Bulk Capacitors: These are high-value electrolytic or tantalum capacitors (e.g., 100 µF to 1000 µF) placed near the VRM. They provide charge for low-frequency current demands (from DC to ~100 kHz) and handle large, sustained current changes [1].
• Mid-Frequency Ceramic Capacitors: Multi-layer ceramic capacitors (MLCCs) with values typically ranging from 0.1 µF to 10 µF are distributed across the PCB, closer to the ASIC package. Their placement and associated mounting inductance are critical, as the effective inductance forms a resonant circuit with the capacitor. The primary decoupling mechanism in this regime becomes the PCB's intrinsic power-ground plane capacitance, which acts as a distributed parallel-plate capacitor [14]. Designers optimize this by using thin dielectric layers between adjacent power and ground planes, which can provide hundreds of picofarads per square centimeter. Additionally, small-form-factor, low-ESL ceramic capacitors (e.g., 01005 or 0201 packages with values of 0.01 µF to 0.1 µF) are placed directly at the ASIC package power balls to mitigate very high-frequency transients.

### Static IR Drop Analysis

In addition to AC impedance, the PDN must be designed to minimize static (DC) IR drop, which is the voltage loss due to the resistance of power planes, traces, and vias between the VRM and the load. Excessive IR drop reduces the effective supply voltage at the ASIC, potentially causing timing failures or functional errors. As established, limits for this drop are typically 5-10% of Vdd [5, 8, 11]. Analysis involves modeling the resistive network of the PCB's copper layers and calculating the voltage at each node under worst-case current draw conditions. Mitigation techniques include:

• Widening power traces and using thicker copper layers (e.g., 2 oz/ft² instead of 1 oz/ft²)
• Increasing the number of power and ground vias in parallel, especially under ball grid array (BGA) packages
• Implementing dedicated power planes with minimal splits or cutouts

### Tools and Methodologies for PDN Design

The analysis and design of board-level power integrity rely heavily on specialized electronic design automation (EDA) tools. These tools extract parasitic RLC networks from PCB layouts and perform frequency-domain impedance simulations and time-domain transient analyses. A key input for accurate simulation is the current profile of the ASIC, often provided by the chip designer as a current waveform (I(t)) or a set of frequency-domain target impedances. Furthermore, the IEEE Xplore digital library serves as a primary repository for research on advanced PDN modeling techniques, material characterization for high-frequency dielectrics, and novel decoupling capacitor optimization algorithms [7, 15].

### Integration with Package and On-Die Power

Board-level power design cannot be isolated; it is the first stage of a cascaded PDN that includes the package and the on-die power grid. The board PDN impedance interacts with the package inductance and on-die capacitance, creating complex resonances. Therefore, co-design and co-simulation across these domains are essential. The board must present a sufficiently low impedance at the package pins so that the combined system meets the target impedance at the silicon transistors. This often involves creating a unified RLC model that spans from the VRM on the board to the standard cells on the die, enabling holistic optimization.

### Verification and Measurement

Final verification involves both simulation and physical measurement. Post-layout simulation of the full board with extracted parasitics confirms that impedance and IR drop targets are met. After board fabrication, measurements are taken using vector network analyzers (VNAs) to characterize the actual PDN impedance profile and time-domain reflectometry (TDR) to assess transmission line quality. Any discrepancies between simulation and measurement are used to refine models for future designs, closing the iterative design loop that is characteristic of robust ASIC implementation.

References

1. MyHDL - https://www.myhdl.org/
2. 1076.1-2017 - IEEE Standard VHDL Analog and Mixed-Signal Extensions - https://ieeexplore.ieee.org/document/8267464
3. Verilog-AMS - https://semiengineering.com/knowledge_centers/standards-laws/standards/verilog-ams/
4. Verdi Automated Debug System | Synopsys - https://www.synopsys.com/verification/debug/verdi.html
5. Hardware Description Languages: VHDL vs Verilog, and Their Functional Uses - https://resources.pcb.cadence.com/blog/2020-hardware-description-languages-vhdl-vs-verilog-and-their-functional-uses
6. Knowledge Booster Training Bytes - How to Model Analog Blocks with Verilog-AMS Wreal Modeling? - https://community.cadence.com/cadence_blogs_8/b/cic/posts/knowledge-booster-training-bytes---how-to-model-analog-blocks-with-verilog-ams-wreal-modeling-1377777914
7. Netlist database - https://patents.google.com/patent/US7231623B2/en
8. Difference between .cdl and .gds files - https://www.edaboard.com/threads/difference-between-cdl-and-gds-files.342204/
9. KARL and ABL - https://link.springer.com/chapter/10.1007/978-94-011-1914-6_16
10. Verilog HDL and its ancestors and descendants (HOPL IV - Papers) - HOPL IV - https://pldi21.sigplan.org/details/hopl-4-papers/6/Verilog-HDL-and-its-ancestors-and-descendants
11. A Brief History of VHDL - https://www.doulos.com/knowhow/vhdl/a-brief-history-of-vhdl/
12. Design circuit boards blazing fast with code - https://atopile.io/
13. [PDF] realBehavModelsSlidesNotes1 - http://www.analogcircuitworks.com/wordpress_acw2010/wp-content/uploads/realBehavModelsSlidesNotes1.pdf
14. Circuit design language - https://grokipedia.com/page/circuit_design_language
15. A Brief History of Verilog - https://www.doulos.com/knowhow/verilog/a-brief-history-of-verilog/
16. GitHub - devbisme/skidl: SKiDL is a library that lets you design electronic circuits using Python. - https://github.com/devbisme/skidl
17. systemc.org - https://systemc.org/overview/systemc/
18. Electric VLSI Design System User's Manual - https://www.staticfreesoft.com/jmanual/mchap07-03-06.html