Nanosheet Field-Effect Transistor

A Nanosheet Field-Effect Transistor (NSFET) is an advanced type of metal-oxide-semiconductor field-effect transistor (MOSFET) and a specific implementation of the gate-all-around (GAA) architecture, where the channel through which current flows is composed of multiple, ultra-thin, horizontal sheets of semiconductor material completely surrounded by the gate electrode [3][8]. This structure represents a significant evolution in transistor design for complementary metal-oxide-semiconductor (CMOS) technology, developed to overcome the scaling limitations of earlier planar and FinFET designs as semiconductor nodes shrink to 3 nanometers and below [1][6]. As a foundational component for ultra-high-density large-scale integration (LSI), NSFETs are classified as multi-gate or surrounding-gate transistors and are critical for continuing Moore's Law by enabling higher performance and lower power consumption in integrated circuits [4][7]. The defining characteristic of a nanosheet FET is its gate-all-around configuration, which provides superior electrostatic control over the channel compared to planar transistors or even FinFETs [2][7]. In this design, the gate material envelops the channel on all sides, dramatically increasing the surface area of contact between the gate and the channel [2][3]. This enhanced control allows for more effective modulation of the channel's conductivity, leading to a steeper subthreshold slope, significantly reduced off-state current leakage, and improved immunity to short-channel effects, which are major challenges at extremely small dimensions [2][4]. The channel itself is typically formed from a stack of silicon or silicon-germanium sheets, each only a few nanometers thick, which are released from a sacrificial layer during fabrication. Key variations in GAA architectures include nanowire FETs, which use cylindrical channels, and the nanosheet or nanoribbon FET, which uses wider, sheet-like channels to provide higher drive current [7][8]. Nanosheet transistors are primarily applied in high-performance computing, mobile systems-on-a-chip (SoCs), and other advanced microprocessors and memory chips where density, power efficiency, and speed are paramount [6]. Their development and commercialization mark a pivotal step in the semiconductor industry's roadmap, with major technology companies introducing them at the 3nm node and beyond [3][6]. For instance, a 5nm test chip demonstrated by IBM, Samsung, and GlobalFoundries was among the first integrated circuits to utilize GAAFET topology [5]. The transition to nanosheet architectures from FinFETs is driven by the need for continued dimensional scaling where the flexibility of fin dimensions in standard cell designs becomes constrained [1]. As the successor to the FinFET era, the nanosheet FET is a cornerstone technology for enabling future generations of artificial intelligence hardware, data centers, and low-power mobile devices, representing a critical innovation in the pursuit of more powerful and energy-efficient electronic systems [6][7].

Overview

The nanosheet field-effect transistor (NSFET) represents a fundamental architectural evolution in metal-oxide-semiconductor field-effect transistor (MOSFET) design, classified under the broader category of gate-all-around field-effect transistors (GAAFETs). This transistor topology addresses critical scaling limitations encountered by its predecessor, the fin field-effect transistor (FinFET), by employing multiple, horizontally stacked, nanometer-thick silicon channels that are completely surrounded by the gate electrode [13][14]. This structural innovation provides superior electrostatic control of the channel, which is paramount for continued device miniaturization and performance enhancement as semiconductor technology advances toward the 3nm node and beyond [13].

Fundamental Architecture and Electrostatic Control

The defining characteristic of the NSFET is its multi-layered channel structure. Unlike the FinFET's vertical fin, which is gated on three sides (tri-gate), the NSFET utilizes several ultra-thin, sheet-like silicon channels stacked vertically on top of one another [14]. Each individual nanosheet, with a thickness typically targeted below 10 nanometers, is fully encircled by the gate dielectric and gate metal, creating a true gate-all-around configuration [13][14]. This geometry maximizes the surface area of interaction between the gate and the channel. The enhanced gate-to-channel coupling provides more effective suppression of short-channel effects, such as drain-induced barrier lowering (DIBL) and subthreshold swing degradation, which become severe at extremely scaled gate lengths [13]. Consequently, NSFETs exhibit significantly reduced off-state leakage current (I_off) compared to both planar FETs and FinFETs at equivalent technology nodes, leading to substantial improvements in power efficiency [13]. The electrostatic advantage can be quantified by considering the natural length (λ) concept, a scaling metric that describes the extent of gate control. For a multi-bridge channel or nanosheet structure, the natural length is approximated by λ ≈ √((ε_ch

• T_ch
• T_ox) / (4ε_ox)), where ε_ch and ε_ox are the dielectric constants of the channel and oxide, respectively, T_ch is the channel thickness, and T_ox is the oxide thickness. The gate-all-around geometry minimizes λ, indicating superior immunity to short-channel effects. This allows for more aggressive scaling of the physical gate length (L_g) while maintaining acceptable performance, as the requirement L_g > 5-10λ can be met with smaller L_g values.

Design Flexibility and Performance Tuning

A key operational benefit of the NSFET architecture is the independent tunability of critical device parameters. The primary design knobs include:

• Nanosheet Width (W_NS): The lateral dimension of each sheet, which directly modulates the drive current. Wider nanosheets provide a larger effective channel width (W_eff = 2
  • N
  • W_NS, where N is the number of stacked sheets), thereby increasing on-current (I_on) [14].
• Nanosheet Thickness (T_NS): The vertical dimension of each sheet, which is a primary lever for adjusting the device's threshold voltage (V_th) and controlling quantum confinement effects. Thinner sheets provide better electrostatic control but may increase carrier scattering.
• Number of Stacked Nanosheets (N): The count of vertically integrated channels, which multiplicatively increases the total drive current for a given footprint without increasing the device's layout width [14]. This multi-dimensional parameter space offers circuit designers greater flexibility to optimize the trade-off between performance (I_on), dynamic power, and leakage power (I_off) for different circuit blocks within a system-on-chip (SoC) [14]. For instance, high-performance logic cores can utilize wider and/or more numerous nanosheets, while always-on, low-power domains might employ narrower or fewer sheets to minimize leakage.

Evolution from FinFET and Scaling Challenges

The NSFET emerges as a solution to specific limitations inherent in the FinFET architecture as scaling progresses. In FinFETs, the channel width is quantized by the fin height and the number of fins. Increasing drive current requires adding more fins, which increases the device's layout footprint [13]. More critically, the evolution of standard cell libraries to lower track heights (e.g., from 12-track to 6-track or 5-track cells) to improve density places stringent constraints on the maximum allowable fin height [13]. This restricts the available channel width per fin, limiting current drive and creating a performance bottleneck. The NSFET circumvents this issue by decoupling the effective channel width from the vertical cell height; width is controlled by the lateral nanosheet dimension (W_NS), which can be adjusted independently of the cell's vertical pitch [13][14]. The fabrication of NSFETs, however, introduces significant process complexities. The manufacturing flow involves epitaxial growth of alternating silicon and silicon-germanium (SiGe) layer stacks, precise patterning to form nanosheet ridges, selective etching of the sacrificial SiGe layers to release the silicon nanosheets, and the subsequent deposition of a uniform gate stack around each free-standing sheet [14]. This inner spacer formation and channel release process is highly sensitive and requires atomic-level precision to ensure mechanical stability, strain engineering, and uniform electrical characteristics across all sheets in the stack.

Electrical Characteristics and Variability

The gate-all-around electrostatics of the NSFET lead to distinct electrical characteristics. The subthreshold swing (SS) approaches the ideal thermal limit of 60 mV/decade at room temperature more closely than in FinFETs, enabling steeper switching. The transconductance (g_m) is also enhanced due to the improved gate coupling. However, new sources of variability emerge:

• Line Edge Roughness (LER) and Width Quantization: Variations in the etched nanosheet width directly affect W_eff and V_th.
• Thickness Variation: Fluctuations in the epitaxial growth and etch processes lead to non-uniform nanosheet thickness (T_NS), impacting V_th and carrier mobility.
• Stress and Strain: The strain in each nanosheet, which is used to boost carrier mobility, can vary depending on its position in the stack and the surrounding materials, leading to performance mismatch between sheets. These variability factors must be meticulously controlled to ensure yield and predictable circuit performance at advanced nodes.

Future Outlook and Integration

As noted earlier, the development of GAAFET technology marks a pivotal step in the semiconductor roadmap. The NSFET is the first mainstream incarnation of this topology. Looking forward, further scaling may lead to evolutionary designs such as the complementary field-effect transistor (CFET), which involves vertically stacking n-type and p-type NSFETs, or the transition to even more confined channel structures like nanowires. The success of the NSFET platform hinges on continuous advancements in materials science (e.g., high-k dielectrics, metal gate work function tuning), process control, and design-technology co-optimization (DTCO) to fully exploit its advantages for future generations of integrated circuits [13][14].

Historical Development

The historical development of the nanosheet field-effect transistor (NSFET) is rooted in the continuous scaling of complementary metal-oxide-semiconductor (CMOS) technology and the fundamental need to overcome the physical limitations of preceding transistor architectures. Its evolution represents a logical progression from planar bulk transistors to three-dimensional (3D) structures, driven by the imperative for enhanced electrostatic control at ever-shrinking process nodes.

Foundations in Planar and Early 3D Transistors

The modern era of integrated circuits was enabled by the development of the planar process in the late 1950s and early 1960s [14]. This manufacturing technique, pioneered by Jean Hoerni at Fairchild Semiconductor with his 1959 patent for the planar transistor, allowed for the fabrication of transistors on a flat silicon surface [14]. This innovation was critical, as it opened the doors to mass-produced monolithic silicon ICs by enabling the precise deposition and patterning of multiple layers, a cornerstone of Robert Noyce's subsequent integrated circuit patent [14]. For over four decades, the industry followed Moore's Law by scaling down these planar field-effect transistors (FETs). However, as channel lengths diminished below approximately 25 nm, severe short-channel effects (SCEs)—such as drain-induced barrier lowering (DIBL) and increased subthreshold leakage—degraded performance and increased power consumption, marking the end of the planar transistor's scalability [14]. This challenge precipitated the transition to three-dimensional transistor designs. The FinFET, first demonstrated by researchers at the University of California, Berkeley in the late 1990s and commercially introduced by Intel at the 22 nm node in 2011, represented the first major architectural shift [14]. By raising the channel into a vertical "fin" wrapped on three sides by the gate, the FinFET provided significantly improved electrostatic control over the channel compared to its planar predecessor. As noted earlier, this increased surface area between the gate and channel translates to better electrostatic control and reduced leakage [14]. The FinFET architecture successfully extended CMOS scaling through the 16/14 nm, 10 nm, and 7 nm process nodes across the industry.

The Drive Toward Gate-All-Around Architectures

Despite its success, the FinFET itself faced scaling limitations as technology nodes advanced to 5 nm and below. A primary constraint emerged from the evolution of standard cell designs toward lower track heights to improve density [14]. This trend left less flexibility in fin dimensions, particularly fin height, making it difficult to further increase drive current (I_ON) by simply making fins taller without violating design-rule constraints. Furthermore, at extremely scaled fin pitches and widths, controlling variability and maintaining sufficient gate control from only three sides became increasingly difficult. These limitations catalyzed research into the gate-all-around (GAA) FET concept, a more radical 3D structure where the gate material completely surrounds the channel, offering the ultimate in electrostatic control [14]. The theoretical superiority of GAA structures was long recognized, with early research on silicon nanowire transistors exploring the concept. The transition to a manufacturable, high-performance GAA architecture suitable for high-volume production became the next critical hurdle. As discussed in prior sections, the industry's first integrated circuits utilizing GAAFET topology emerged in test chips at the 5 nm node, paving the way for commercialization.

Emergence and Commercialization of the Nanosheet FET

The nanosheet FET emerged as the first mainstream, manufacturable incarnation of the GAA topology, addressing the practical challenges of earlier nanowire concepts by employing wider, stacked silicon channels. This structure involves epitaxially growing alternating layers of silicon and silicon-germanium (SiGe), then selectively removing the SiGe to release multiple horizontal sheets of silicon channel material stacked vertically [14]. Each sheet is fully enveloped by the gate dielectric and gate metal, achieving true gate-all-around control. The key advantage of the nanosheet over the FinFET is the ability to independently tune the channel width via the nanosheet width (W_NS), providing a powerful new design knob for optimizing the current drive per footprint without being constrained by fixed fin geometries [14]. Building on the concepts discussed above, this parameter, along with the nanosheet thickness (T_NS) and the number of stacked sheets, allows designers to tailor performance, power, and area (PPA) for different circuit applications. The superior electrostatic control inherent to the GAA design results in a steeper subthreshold swing, which, as mentioned previously, approaches the ideal thermal limit more closely than in FinFETs, enabling lower operating voltages and reduced dynamic power [14]. Major semiconductor foundries introduced NSFETs at their 3 nm-class process nodes. Samsung Electronics was the first to announce volume production of its "3GAE" (3 nm Gate-All-Around Early) node using multi-bridge-channel FET (MBCFET™), its branded NSFET technology. Taiwan Semiconductor Manufacturing Company (TSMC) followed with its "N3B" and subsequent "N3E" nodes, which are based on FinFETs, but has slated its GAA-based "N2" (2 nm) node for future introduction, featuring nanosheet transistors. Intel's roadmap refers to its GAA technology as "RibbonFET," which is central to its post-FinFET nodes [15].

Roadmap and Future Trajectory

The development and introduction of NSFETs represent a pivotal step, but the historical progression of transistor technology is an ongoing process. These GAA structures are designed to carry through the advanced process nodes currently on the industry roadmap [14]. Intel, for instance, has confirmed its "18A" (1.8 nm-class) node, featuring its RibbonFET and PowerVia backside power delivery, is slated for high-volume manufacturing later in 2024, with client products like "Panther Lake" CPUs expected in the second half of 2025 [15]. Looking further ahead, Intel's "Nova Lake" architecture is planned for 2026, and development is underway on "14A" (1.4 nm-class) and more advanced nodes, which promise increased performance-per-watt and density scaling [15]. The historical path suggests continued evolution within the GAA framework. To further enhance performance and density for nodes beyond 2 nm, the industry is actively researching complementary FET (CFET) architectures, which involve stacking n-type and p-type nanosheets vertically on top of each other. Furthermore, the integration of new channel materials with higher electron mobility than silicon, such as germanium or III-V compounds, into the nanosheet structure is a subject of intensive research, potentially marking the next significant inflection point in the historical development of the field-effect transistor.

Principles of Operation

The operational principles of the nanosheet field-effect transistor (NSFET) are fundamentally governed by its three-dimensional gate-all-around (GAA) architecture, which provides superior electrostatic control over the transistor channel compared to preceding planar and FinFET technologies. This enhanced control is critical for enabling continued device scaling as defined by Moore's Law, particularly at sub-4 nm process nodes where FinFETs face fundamental limitations in gate voltage scaling [3]. The NSFET's operation can be analyzed through its electrostatics, carrier transport, and the impact of its key geometric parameters on electrical characteristics.

Electrostatic Control and Short-Channel Effects

The primary operational advantage of the NSFET stems from its GAA structure, where the gate electrode completely surrounds the channel on all four sides. This geometry maximizes the gate-to-channel capacitive coupling, significantly suppressing short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL) and subthreshold leakage. The electrostatic integrity of a transistor is often quantified by its natural length (λ), a scaling metric that describes the penetration of drain electric fields into the channel. For a rectangular nanosheet, this can be approximated by:

$$\lambda \approx \sqrt{\frac{\epsilon_{ch}}{\epsilon_{ox}} \cdot T_{ch} \cdot T_{ox}}$$

where:

• $\epsilon_{ch}$ is the dielectric constant of the channel material (typically ~11.7 for silicon)
• $\epsilon_{ox}$ is the dielectric constant of the gate oxide (e.g., ~25 for HfO₂)
• $T_{ch}$ is the nanosheet thickness, typically ranging from 5 nm to 10 nm in advanced nodes
• $T_{ox}$ is the equivalent oxide thickness (EOT), which can be scaled to ~0.5 nm or less [16]

A smaller λ indicates better immunity to SCEs. The GAA topology minimizes λ by providing gate control from multiple surfaces, allowing for more aggressive scaling of the physical gate length ($L_g$) while maintaining acceptable off-state leakage. This is a direct evolution from the planar process, which enabled monolithic integration but faced severe SCEs at short $L_g$ [2], and the FinFET, which improved control via a tri-gate structure but leaves one channel surface uncontrolled.

Carrier Transport and Current Drive

Current conduction in an NSFET occurs through multiple, vertically stacked silicon nanosheets that act as parallel conduction paths. The total drive current ($I_{on}$) in the linear region can be modeled as:

$$I_{on} \approx \mu_{eff} \cdot C_{ox} \cdot \frac{W_{eff}}{L_g} \cdot (V_{gs} - V_{th}) \cdot V_{ds}$$

where:

• $\mu_{eff}$ is the effective carrier mobility (electrons or holes), typically 200–500 cm²/V·s for electrons in strained silicon
• $C_{ox}$ is the gate oxide capacitance per unit area
• $W_{eff}$ is the total effective channel width, given by $W_{eff} = 2 \cdot N \cdot (W_{NS} + T_{NS})$, where $N$ is the number of stacked nanosheets
• $V_{gs}$, $V_{th}$, and $V_{ds}$ are the gate-to-source, threshold, and drain-to-source voltages, respectively

The nanosheet width ($W_{NS}$) is a critical design parameter that modulates $I_{on}$ and is adjustable post-fabrication, offering design flexibility not present in FinFETs where fin width is fixed. Wider sheets provide greater drive current but can degrade electrostatic control. The multi-sheet design allows $W_{eff}$ to be increased vertically within a fixed footprint, improving current density per layout area—a key requirement for standard cell scaling [13].

Threshold Voltage Modulation and Quantum Confinement

The nanosheet thickness ($T_{NS}$) is a primary lever for setting the transistor's threshold voltage ($V_{th}$), a fundamental parameter determining switching behavior. In ultra-thin silicon bodies, quantum confinement effects become significant, leading to a widening of the band gap and a consequent increase in $V_{th}$. The shift in threshold voltage due to quantization ($\Delta V_{th,qc}$) can be estimated by:

$$\Delta V_{th,qc} \approx \frac{\hbar^2 \pi^2}{2 q m^* T_{NS}^2}$$

where:

• $\hbar$ is the reduced Planck's constant
• $q$ is the elementary charge
• $m^*$ is the carrier effective mass (e.g., ~0.19$m_0$ for electrons in silicon)

This allows $V_{th}$ to be tuned by varying $T_{NS}$ across different device types (e.g., high-performance vs. low-power) on the same chip. Furthermore, the GAA structure enables the use of multiple, independent gate materials or workfunction metals to precisely engineer $V_{th}$ without relying solely on channel doping, which is beneficial for mitigating variability.

Gate Stack and Advanced Materials

The gate stack in an NSFET is a critical component for its operation. It typically consists of an interfacial layer (e.g., SiO₂), a high-κ dielectric (predominantly HfO₂ with a κ ~25), and a metal gate electrode. The gate capacitance is given by:

$$C_{ox} = \frac{\epsilon_0 \kappa}{T_{phys}}$$

where $T_{phys}$ is the physical thickness of the dielectric. Achieving a low equivalent oxide thickness (EOT) while managing gate leakage is essential. The conformal deposition of these layers around the nanosheet is a key process challenge in the front-end-of-line (FEOL) [6]. Research into negative-capacitance FETs (NCFETs) explores integrating a ferroelectric layer, such as doped HfO₂, within this stack to achieve a sub-60 mV/decade subthreshold swing, though integration is challenging in scaled gate-last processes due to space constraints [16].

Scalability and Roadmap

The operational principles of the NSFET are designed to support continued scaling along the advanced logic roadmap [1]. As noted earlier, the architecture overcomes the gate control limitation encountered by FinFETs at the sub-4 nm node [3]. The ability to separately optimize $W_{NS}$ and $T_{NS}$ provides multiple knobs for performance-power-area (PPA) trade-offs, making NSFETs a versatile platform for future nodes. Their development represents a logical progression from the planar transistors that enabled mass-produced integrated circuits [2], and their GAA foundation is expected to carry forward to even more advanced transistor topologies.

Types and Classification

The classification of nanosheet field-effect transistors (NSFETs) can be approached from multiple dimensions, including architectural implementation, channel material composition, integration scheme, and performance target. These classifications are often defined by the specifications of advanced process design kits (PDKs) from major foundries and the ongoing research roadmap for complementary metal-oxide-semiconductor (CMOS) technology.

By Architectural Implementation and Channel Geometry

The most fundamental classification distinguishes between different gate-all-around (GAA) transistor topologies based on the shape and arrangement of the channel material. Beyond the basic nanosheet structure, several architectural variants exist, primarily differentiated by the cross-sectional geometry of the channel.

• Nanosheet FETs (NSFETs): This is the predominant commercial GAA architecture, characterized by multiple, horizontally stacked, flat silicon channels fully surrounded by the gate dielectric and metal gate [17]. The width of each sheet (W_NS) is a critical design parameter that modulates drive current, while the thickness (T_NS) controls threshold voltage [21]. This structure provides a larger effective channel width per footprint compared to FinFETs, improving drive current and density [21].
• Nanowire FETs (NWFETs): A related GAA architecture where the channel takes the form of one or more cylindrical or nearly cylindrical silicon wires. The diameter of the nanowire is a key scaling and performance parameter. Research has shown that varying the nanowire diameter and gate insulator thickness are crucial structural parameters for optimizing performance metrics like the Ion/Ioff ratio [16]. NWFETs typically offer the ultimate in electrostatic control due to their small, uniform cross-section but may have lower total drive current per footprint than wider nanosheets.
• Forksheet FETs: An evolutionary architecture proposed for nodes beyond the initial NSFET introduction. In this configuration, n-type and p-type nanosheets are placed in closely spaced but separate trenches, allowing for a reduction in the spacing between NMOS and PMOS transistors within a standard cell, thereby improving logic density.
• Complementary FET (CFET): This represents a more advanced, three-dimensional integration of GAA structures where n-type nanosheets are stacked directly on top of p-type nanosheets (or vice versa) within a single device footprint. This vertical co-integration aims to dramatically increase transistor density by effectively halving the cell footprint for a CMOS pair.

By Channel Material

While initial commercial NSFETs utilize silicon channels, significant research and development is focused on integrating high-mobility materials to boost performance, leading to a material-based classification.

• Silicon (Si) NSFETs: The current industry standard, leveraging mature silicon processing. Performance is tuned through geometric parameters and strain engineering.
• Silicon-Germanium (SiGe) NSFETs: SiGe, particularly for p-channel transistors (PFETs), offers higher hole mobility than silicon, which can translate to higher drive current and speed. Integration often involves SiGe channels or raised source/drain regions.
• Germanium (Ge) NSFETs: Germanium provides very high electron and hole mobility. However, challenges related to high-quality gate dielectric formation and junction leakage have limited its commercial adoption in mainstream logic, though it remains an active research area.
• III-V Compound Semiconductor NSFETs: Materials like Indium Gallium Arsenide (InGaAs) are investigated for n-channel devices due to their exceptionally high electron mobility. These are primarily considered for heterogeneous integration on silicon platforms for specific high-performance or low-power applications.

By Integration and Packaging Scheme

NSFETs are integrated into larger systems following specific paradigms, which classify the final chip architecture.

• Planar Monolithic Integration: The traditional approach, where all transistors and interconnects are fabricated on a single, flat silicon substrate. This method benefits from the established, high-yield planar process that enabled mass-produced monolithic integrated circuits [7].
• 2.5D and 3D Integrated Systems: Advanced packaging techniques that employ NSFET-based chiplets or dies. In 2.5D integration, multiple chips are arranged on a passive or active interposer, which provides high-density wiring for communication between them [20]. In 3D integration, tiers of NSFETs are stacked vertically and connected with through-silicon vias (TSVs), offering the highest density and shortest interconnect paths.

By Application and Performance Node

Foundries define process nodes (e.g., 3nm, 2nm) with specific performance, power, and density targets. NSFETs are classified by the node at which they are introduced and the primary application domain they target.

• Leading-Edge Logic Nodes: NSFET technology was first introduced for high-volume manufacturing at the 3 nm-class node [17][7]. Subsequent nodes, such as TSMC's N2, are designed to deliver performance gains of 10–15% at iso-power or power reductions of 25–30% at iso-performance compared to their predecessors [19]. These nodes target advanced CPUs, GPUs, and mobile SoCs. For instance, a mobile processor utilizing a 3 nm-class GAA process has demonstrated a 39% improvement in on-device AI compute capability over its predecessor [18].
• Specialized Technology Variants: Foundries often offer tailored versions of a base node. These can include:
• High-Performance (HP) libraries: Optimized for maximum frequency in critical paths, often using different nanosheet dimensions (e.g., wider sheets for higher current) and middle-of-line/interconnect optimizations.
• High-Density (HD) libraries: Optimized for area efficiency in memory arrays (SRAM) and logic where speed is less critical, potentially using tighter pitches and different cell architectures.
• Ultra-Low-Power (ULP) libraries: Designed for always-on or battery-sensitive applications, emphasizing leakage reduction through specific threshold voltage adjustments and possibly different channel geometries. The progression of these GAA-based architectures is expected to carry through the advanced process nodes currently on the industry roadmap, becoming the standard for advanced logic chips used in applications from artificial intelligence to high-performance computing [19][7]. The classification continues to evolve as the technology matures and new variants, like CFET, move from research to development.

Key Characteristics

The transition to the gate-all-around (GAA) architecture represents a fundamental shift in transistor design, primarily engineered to overcome the physical and electrical limitations of the FinFET structure at advanced technology nodes [20]. This architectural change introduces a new set of defining electrical and structural properties that govern device performance, manufacturability, and application.

Architectural Superiority and Electrostatic Control

The defining feature of the nanosheet field-effect transistor (NSFET) is its gate-all-around structure, where the gate material fully encircles the channel on all sides [20]. This provides superior electrostatic control over the channel compared to the tri-gate configuration of a FinFET, where the gate contacts only three sides of the fin [21]. The enhanced control directly mitigates short-channel effects (SCEs), which become increasingly problematic as physical dimensions shrink below 5 nm. Improved electrostatic integrity results in a sharper turn-on characteristic, allowing for more effective switching at lower voltages [8]. This architectural advantage is the principal reason the semiconductor industry is adopting GAAFETs to replace FinFETs at the 3 nm node and below, as it addresses the core scaling challenges that FinFETs can no longer overcome [8][9].

Performance and Power Scaling at Advanced Nodes

The implementation of GAA architecture is intrinsically linked to the progression of semiconductor process nodes. As noted earlier, major foundries have introduced this technology at 3 nm-class nodes [17]. The performance claims for these new processes are substantial. For example, TSMC's N2 (2nm-class) process, its first to utilize GAA transistors, claims performance improvements of 10% to 15% at the same power, or power reductions of 25% to 30% at the same performance, compared to its preceding N3E node [19]. This scaling benefit is critical for continued Moore's Law progression. Samsung's 3nm GAA process, branded as 3GAE, similarly promises a 23% performance increase, a 45% reduction in power consumption, and a 16% smaller area compared to its 5nm FinFET process [17]. These gains are not merely incremental but are essential for enabling next-generation computing, particularly for mobile and AI applications where power efficiency is paramount [18].

Structural Parameter Tuning and Device Optimization

Unlike FinFETs, where the fin height and width are the primary design parameters, NSFETs introduce a more versatile set of structural knobs for device optimization. While the width and thickness of individual nanosheets are critical, as previously mentioned, the architecture allows for additional tuning. Analytic simulations characterize device performance by varying parameters such as the nanosheet diameter (or width) and the thickness of the gate insulator [4]. This enables engineers to tailor the transistor's electrical characteristics—such as drive current (I_ON), off-state leakage (I_OFF), and threshold voltage (V_th)—for specific circuit applications. The ability to independently adjust multiple geometric factors provides greater flexibility to meet the diverse performance, power, and density requirements of modern system-on-chips (SoCs).

Enabling Advanced On-Device AI and Mobile Processing

The performance and efficiency gains of NSFET technology are directly leveraged to enable more powerful and complex on-device computing. Building on the AI compute improvements mentioned previously, the architectural benefits of GAAFETs are crucial for mobile processors that handle increasing AI workloads. For instance, the Exynos 2500 mobile processor, designed to utilize advanced process technology, aims to provide secure, on-device AI access from anywhere, which necessitates both high performance and exceptional power efficiency [18]. The transistor's improved switching characteristics and lower operating voltages directly contribute to longer battery life while enabling more sophisticated neural network inference directly on the smartphone, enhancing user privacy and responsiveness [18].

Foundry Competition and Production Milestones

The development and production of NSFETs signify a key competitive battleground for leading semiconductor foundries. Samsung was the first to announce volume production of 3nm chips using its multi-bridge-channel FET (MBCFET™) technology, a specific implementation of the nanosheet GAAFET [17]. This move marked a significant milestone in the commercialization of GAA transistors. Subsequently, TSMC has begun volume production of chips using its N2 process, representing its inaugural use of GAA transistors [19]. This competitive rollout underscores the industry-wide consensus on the necessity of GAA architecture for continued scaling and highlights the intense pace of innovation and capital investment required at the frontier of semiconductor manufacturing [19][8].

Design Challenges and Future Outlook

The adoption of GAAFETs introduces a new set of challenges for integrated circuit design teams that must be fully understood and addressed [8]. These challenges include:

• Parasitic Extraction and Modeling: The three-dimensional complexity of stacked nanosheets, with intricate spacer regions and source/drain epitaxy, makes accurate parasitic capacitance and resistance extraction more difficult than with FinFETs [8].
• Process Variation: Variability in nanosheet width, thickness, and spacing can have a significant impact on circuit performance and yield, requiring more robust design methodologies [8].
• Standard Cell and PDK Development: Design kits and standard cell libraries must be completely re-characterized for the new transistor architecture, affecting everything from logic synthesis to physical design and timing closure [8]. Despite these challenges, the industry is poised for this structural change, viewing it as a necessary step to extend CMOS scaling [8][9]. The node, defined by its performance specifications, process technology, and design rules, reaches a tipping point at 3nm where a transistor architecture change becomes mandatory [9]. As production matures at 3nm and 2nm-class nodes, further innovations in nanosheet design—such as complementary FET (CFET) configurations and the integration of new channel materials—are anticipated to drive the next phase of performance improvements [20][8].

Applications

The introduction of nanosheet field-effect transistors (NSFETs) represents a strategic response to the scaling limitations of FinFET technology, which began to fall short of industry expectations as dimensions approached the sub-5nm regime [11][25]. This transition enables a new paradigm in semiconductor design, moving beyond the performance-density trade-offs inherent to previous architectures and unlocking targeted optimization for diverse application domains [22]. The fundamental shift lies in the transition from a single, fixed scaling "knob"—fin-height scaling in FinFETs—to a multi-dimensional design space. In the FinFET era, standard-cell layouts could be scaled without altering the track pitch by reducing the number of fins while simultaneously increasing fin height. This approach, however, necessitated distinct process flows for wide, high-performance devices and narrow, low-power devices, complicating design and integration [25]. NSFETs overcome this constraint by providing independent control over channel width through the number and dimensions of stacked nanosheets, allowing for performance and power characteristics to be tuned within a unified process technology [10].

Enabling Continued Scaling and Performance Gains

The primary application of NSFET technology is to sustain the historical trajectory of Moore's Law by enabling continued transistor miniaturization and performance improvement in the face of significant physical and technical challenges [23]. As feature sizes shrink, traditional planar and FinFET architectures struggle with short-channel effects, degraded gate control, and severe power-performance trade-offs [22]. The gate-all-around (GAA) structure of the NSFET provides superior electrostatic control of the channel compared to FinFETs, which is critical for maintaining device functionality and efficiency at atomic-scale dimensions [24]. This enhanced control directly addresses the limitations that signaled the end of the FinFET's scalability [11]. Consequently, NSFETs form the foundation for advanced process nodes, such as 3nm and 2nm, where they are instrumental in delivering the industry's perpetual pursuit of hardware that is faster, smaller, and more energy-efficient [12]. By defying the performance limitations of FinFETs, NSFET technology improves power efficiency through supply voltage reduction while simultaneously enhancing performance by increasing drive current capability [10].

Domain-Specific Circuit Optimization

A key advantage of the NSFET's adaptable structure is its ability to facilitate domain-specific optimization within a single chip or process node. Unlike the FinFET's relatively rigid geometry, the width of NSFET channels can be varied by adjusting the number of stacked nanosheets and their lateral dimensions (W_NS). This creates a versatile "library" of devices with different drive strengths and leakage characteristics without requiring fundamental changes to the fabrication process. Designers can strategically deploy these devices:

• High-Performance Cores: For critical paths in processors (e.g., CPU/GPU cores, AI accelerators), designers can utilize NSFETs configured with a larger number of wider nanosheets. This maximizes the effective channel width (Weff), thereby providing the high drive current necessary for achieving maximum operating frequencies [10].
• Low-Power and Always-On Logic: For non-critical logic, memory peripherals, and always-on domains in mobile and IoT applications, NSFETs with fewer or narrower nanosheets can be implemented. These configurations minimize static leakage current and capacitance, optimizing for ultra-low power consumption and extended battery life.
• Analog/RF Circuits: The superior electrostatic control and the ability to tailor transconductance (gm) and noise characteristics through nanosheet dimensions make NSFETs promising for integrated analog and radio-frequency circuits at advanced nodes, where FinFETs often exhibit performance degradation. This granularity allows for a more optimal power-performance-area (PPA) trade-off across different functional blocks, moving beyond the one-size-fits-all constraint of earlier technologies [22].

Foundry Process Technology and Roadmaps

The adoption of NSFETs is a central element in the competitive roadmaps of leading semiconductor foundries, defining the capabilities of each new technology generation. As the industry progresses, the challenges associated with manufacturing these increasingly complex structures are significant but necessary to overcome for advancing beyond the 3nm mark [26]. Each foundry's implementation features specific optimizations:

• Samsung's MBCFET™: As the first to enter volume production with a 3nm GAA process, Samsung's multi-bridge-channel FET employs nanosheets with a tapered design to alleviate parasitic capacitance and resistance issues. Subsequent iterations aim to further refine sheet profile and introduce new materials.
• TSMC's Nanosheet Technology: Introduced at its N3 node and evolved for N2, TSMC's approach focuses on density and performance scaling, with backside power delivery network (BSPDN) integration being a key differentiator in later nodes to reduce IR drop and improve performance.
• Intel's RibbonFET: Intel's GAA implementation, slated for its 20A node, uses a similar nanosheet (or "nanoribbon") concept, with emphasis on co-optimization with its PowerVia backside power delivery technology. The progression of these nodes is systematically designed to deliver quantifiable gains, such as performance improvements of 10–15% at iso-power or power reductions of 25–30% at iso-performance, as benchmarks for successive generations [12]. These metrics are crucial for end applications in high-performance computing and mobile systems.

Target Markets and End-Use Systems

The performance and efficiency characteristics of NSFETs make them particularly critical for several high-growth and technologically demanding markets:

• Mobile Computing and Smartphones: This remains the primary driver for initial NSFET adoption due to its stringent requirements for energy efficiency, compute density, and thermal management. Processors built on 3nm GAA technologies directly enable longer battery life, more powerful on-device AI processing, and enhanced graphics capabilities within the same or smaller form factors [10][12].
• High-Performance Computing (HPC): Servers, data center CPUs, and AI training chips require the absolute maximum in performance and transistor density. NSFETs provide the path for continued core count increases and clock speed improvements while managing total power consumption and heat dissipation, which are critical constraints in data centers [22][23].
• Artificial Intelligence and Machine Learning: Both edge AI devices and cloud-based training infrastructures benefit from NSFET scaling. The technology enables more efficient and powerful specialized accelerators (TPUs, NPUs) by packing more compute elements into a given area and operating them at lower voltages, improving computations per watt—a key metric for AI [12].
• Automotive and Aerospace: Advanced driver-assistance systems (ADAS), vehicle electrification, and avionics require electronics that are both high-performance and exceptionally reliable. The enhanced control and potential for improved reliability metrics in NSFETs at advanced nodes make them suitable for these demanding environments. In conclusion, the application of nanosheet field-effect transistors extends far beyond a simple transistor replacement. It enables a systemic shift in semiconductor innovation, moving from a focus purely on transistor scaling to a holistic system-technology co-design approach [22]. By providing a flexible, scalable, and high-performance foundation for the angstrom era, NSFET technology is poised to underpin advancements across the entire spectrum of modern electronics, from handheld devices to planetary-scale computing infrastructure.

Design Considerations

The transition from FinFET to nanosheet field-effect transistor (NSFET) architecture introduced a new and more complex set of design variables and trade-offs for semiconductor engineers. While the FinFET's primary geometric control was the fin height and width, the NSFET's gate-all-around (GAA) structure provides multiple, interdependent parameters that must be co-optimized for power, performance, and area (PPA). This multi-dimensional design space requires careful consideration of electrostatic control, quantum mechanical effects, parasitic elements, and manufacturability to fully realize the technology's potential for creating faster, smaller, and more energy-efficient hardware [1][2].

Geometric Parameter Optimization

The functionality of an NSFET is governed by several key geometric parameters that serve as primary design knobs. In addition to the previously discussed nanosheet width (W_NS) and thickness (T_NS), the number of stacked nanosheets (N) is a critical degree of freedom [3]. Stacking multiple sheets vertically increases the total effective channel width (Weff = 2

• N
• W_NS) without consuming additional layout area, directly boosting drive current (Ion). However, increasing N also raises the intrinsic device capacitance and complicates the fabrication process, particularly the epitaxial growth of uniform silicon layers and the subsequent removal of sacrificial layers to form the gate-all-around structure [4]. The nanosheet spacing (T_sp)—the vertical distance between adjacent sheets—must be carefully chosen to balance gate fill capability during deposition against inter-sheet capacitive coupling, which can degrade circuit speed [5]. Another crucial parameter is the gate length (Lg). While scaling Lg improves performance by reducing channel resistance, it also increases short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL). The GAA structure provides superior electrostatic control compared to FinFETs, allowing for more aggressive Lg scaling while maintaining acceptable leakage. For sub-3 nm nodes, Lg is projected to scale below 12 nm, necessitating precise control to manage variability [6]. The inner spacer thickness between the source/drain epitaxy and the gate is also a key design element, as it modulates the parasitic capacitance between the gate and the source/drain (Cgs, Cgd), directly impacting the device's switching speed (fT, fmax) [7].

Electrostatic and Quantum Confinement Trade-offs

The gate-all-around geometry provides nearly ideal electrostatic control, enabling a subthreshold swing (SS) that more closely approaches the theoretical limit. This allows for a reduction in supply voltage (Vdd) while maintaining a sufficient on/off current ratio (Ion/Ioff), a primary pathway to improved power efficiency [8]. However, this benefit interacts with quantum confinement effects. As T_NS is scaled below approximately 5 nm to maintain gate control over short channels, the quantization of electron energy states becomes significant. This quantum confinement increases the effective bandgap of the silicon channel, leading to a rise in threshold voltage (Vth) [9]. Designers must therefore balance T_NS: a thinner sheet improves SCEs but increases Vth and may reduce carrier mobility due to increased surface roughness scattering, while a thicker sheet lowers Vth but degrades electrostatic integrity [10]. The choice of channel material is directly influenced by these trade-offs. While silicon remains the incumbent, strain engineering and alternative channel materials like silicon-germanium (SiGe) or germanium are considered to boost carrier mobility and compensate for performance loss at ultra-thin body dimensions [11]. Furthermore, the work function metal (WFM) stack within the gate electrode requires precise tuning to set the absolute Vth for both NMOS and PMOS devices, a process complicated by the conformal deposition required on the complex 3D nanosheet surfaces [12].

Parasitic and Layout Considerations

A significant portion of the design effort focuses on managing parasitics, which can offset the intrinsic performance gains of the GAA structure. Key parasitic components include:

• Source/Drain Resistance (Rsd): The external resistance associated with the raised source/drain epitaxial regions and the contact metallurgy. As the intrinsic channel resistance decreases with scaling, Rsd constitutes a larger fraction of the total device resistance, limiting Ion gain [13].
• Gate Resistance (Rg): The resistance of the gate electrode itself. With a wrapped gate structure, the total gate perimeter is large, and the use of metal gates is essential to minimize Rg and associated delay (RC delay) [14].
• Parasitic Capacitance: This includes the previously mentioned inner spacer capacitance (Cgs, Cgd) and the fringe capacitance between the gate and the substrate. The complex 3D structure makes accurate extraction and modeling of these capacitances challenging but essential for circuit design [15]. At the standard cell level, the design of NSFETs is constrained by the industry's drive toward lower track heights for improved density. The vertical stacking of nanosheets is advantageous here, as it allows for a wider effective channel within a fixed cell height compared to a multi-fin FinFET layout, improving drive strength per footprint [16]. However, the cell architecture must accommodate the process requirements for the nanosheet release etch and gate formation, potentially imposing new design rules on cell boundaries and neighboring device interactions [17].

Reliability and Variability Challenges

New reliability mechanisms emerge with the NSFET structure. The high-k metal gate materials are subjected to significant mechanical stress due to the different thermal expansion coefficients of the materials in the complex stack, potentially affecting Vth stability over time [18]. The corners of the rectangular nanosheets can create localized electric field enhancements, increasing susceptibility to hot carrier injection and gate oxide degradation [19]. Furthermore, the variability in critical dimensions—such as T_NS, W_NS, and Lg—due to fabrication imperfections is a major concern. Even nanometer-scale variations can lead to significant fluctuations in Vth and Ion, impacting yield and circuit performance predictability. Advanced process control and design techniques, such as adaptive body biasing, are required to mitigate these effects [20].

System-Level Co-Design

Ultimately, the design of NSFETs cannot be isolated from system-level objectives. The technology's promise of improved power efficiency and performance enables architectural innovations in processors and memory. For example, the ability to operate at lower Vdd supports dynamic voltage and frequency scaling (DVFS) for power management, while increased drive current capability can be leveraged for faster cache access or more parallel compute units [21]. Therefore, the optimization of NSFET device parameters is an iterative process informed by circuit performance models and system architecture simulations, ensuring the technology delivers tangible benefits at the application level, from mobile devices to high-performance computing [22].

References

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